JPS5984945U - Input circuit of signal transmission system - Google Patents
Input circuit of signal transmission systemInfo
- Publication number
- JPS5984945U JPS5984945U JP18074182U JP18074182U JPS5984945U JP S5984945 U JPS5984945 U JP S5984945U JP 18074182 U JP18074182 U JP 18074182U JP 18074182 U JP18074182 U JP 18074182U JP S5984945 U JPS5984945 U JP S5984945U
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- circuit
- data
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Selective Calling Equipment (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例の回路構成図、第２図、第３図は同上の
動作説明図のタイムチャート、第４図は本考案の一実施
例の回路構成図、第５図は同上の動作説明図のタイムチ
ャート、第６図は同上応用の伝盗システムの送信ユニッ
トの回路図であり、４は送信制御回路、５はラッチ回路
、６は第１の比較回路、７は第２の比較回路、Ｔｒはト
ランジスタ、ＦＯＲ，ＦＯＲ２は排他的オアである。Figure 1 is a circuit configuration diagram of a conventional example, Figures 2 and 3 are time charts of the same operation explanation diagram, Figure 4 is a circuit configuration diagram of an embodiment of the present invention, and Figure 5 is the same operation as above. The explanatory time chart and FIG. 6 are circuit diagrams of the transmission unit of the robbery system applied to the above, where 4 is a transmission control circuit, 5 is a latch circuit, 6 is a first comparison circuit, and 7 is a second comparison circuit. In the circuit, Tr is a transistor, and FOR and FOR2 are exclusive ORs.
Claims (1)
力データ゛信号を読込んで入力データ信号に基く信号を
伝送するとともに伝送終了後に入力′データ信号と一致
する出力をデータ出力端子より一発生する送信制御回路
を備えた信号伝送システムにおいて、外部入力信号をク
ロックの立上り時にラッチするとともにラッチ出力を前
記送信制御回路のデータ入力端子に出力するラッチ回路
と外部入力信号と前記送信制御回路のデータ出力端子か
−らの出力とを比較する排他的オアを有する第１の比較
回路と、データ出力端子からの出力と前記−ラッチ回路
のラッチ出力とを比較する別の排他的オアを有し、この
排他的オアの出力を送信制御回路のストローブ信号入力
端子に出力するとともに、トランジスタを介して接地す
る第２の比較回路と、送信制御回路から一定周期で出力
する同期信号と第１の比較回路の排他的オアの出力とを
入力して論理積演算を行なってそのゲート出力を上記ラ
ツーチ回路のクロックとするアンドゲートとを備え、前
記送信制御回路から出力する同期信号で上記トランジス
タをオン、オフさせることを特徴とする信号伝送システ
ムの入力回路。A transmission control circuit is provided which reads an input data signal from a data input terminal when a strobe signal rises, transmits a signal based on the input data signal, and generates an output from a data output terminal that matches the input data signal after the transmission is completed. In a signal transmission system comprising: a latch circuit that latches an external input signal at the rising edge of a clock and outputs a latch output to a data input terminal of the transmission control circuit; a first comparator circuit having an exclusive OR for comparing the output from the data output terminal and another exclusive OR for comparing the output from the data output terminal and the latch output of the latch circuit; A second comparator circuit outputs its output to the strobe signal input terminal of the transmission control circuit and is grounded via a transistor, and an exclusive OR of the synchronization signal output from the transmission control circuit at a constant cycle and the first comparator circuit. and an AND gate that performs an AND operation by inputting an output and uses the gate output as a clock for the Latouch circuit, and turns on and off the transistor with a synchronization signal output from the transmission control circuit. Input circuit for signal transmission system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18074182U JPS5984945U (en) | 1982-11-30 | 1982-11-30 | Input circuit of signal transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18074182U JPS5984945U (en) | 1982-11-30 | 1982-11-30 | Input circuit of signal transmission system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5984945U true JPS5984945U (en) | 1984-06-08 |
| JPH0233418Y2 JPH0233418Y2 (en) | 1990-09-07 |
Family
ID=30391817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18074182U Granted JPS5984945U (en) | 1982-11-30 | 1982-11-30 | Input circuit of signal transmission system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5984945U (en) |
-
1982
- 1982-11-30 JP JP18074182U patent/JPS5984945U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0233418Y2 (en) | 1990-09-07 |
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