JPS5988871A - High stabilized low voltage integrated circuit surface breakdown diode structure and method of producing same - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (Invention σ) Previous year) This θ) Subsurface avalanche joint 'a: 4+i
iii) Revised avalanche diode structure (I).

4) From the dislocations caused during the diffusion of the heavily doped region with a similar 1-4V passitance
As a result, the monolithic integrated JFI circuit technology is directly related to the balanzoe and zener junction structure. (formerly known as Tsumata hybrid integrated circuit technology)
4) Great need for avalanche and zener diodes with low commercial stability and low reliability during spring production.
) This 441σ) is very accurate (avalanche or zener diode +Φ push θ) in a precision monolithic stacking circuit and also in a hybrid single push 1st path.
47F has one digital/analog converter (external device, analog/
Digital converter, Ichikawa - Frequency converter, (like switching element of Φ) [In analog equipment,
-1-Tsumatagami tilj's digital circuit.

It is used as a claw. (It should be pointed out here that the terms ``avalanche'' and ``zener'' are often used technically interchangeably; the term ``zener'' is -1 - σ) Class σ) 1) 1
It is more commonly used to refer to the one-junction reverse breakdown mechanism, however, technically it is not a Zener breakdown phenomenon (IRT) but rather a mechanical quantum tunneling phenomenon. Here, The specific yield mechanism that occurs is based on this invention θ
) Since it is unrelated to the formation of tII′f, we will use the term [avalanche] to refer to both of these phenomena. )
Unfortunately, it is difficult to obtain the high degree of stability and low noise required in an avalanche diode, and it introduces at least (12) extra cost and complexity into the integrated circuit manufacturing process. 7':c L is Ogawa-Noh's 3 well-known σ), and usually 0) in monolithic Hayabusa 4'8 circuit elements, the oxide/silicon j has an interface or 0) placed exactly near it. God's form 0) Due to non-conformity, ￥+li matter and/or 1d crystal defect (・C error so-called "surface'fJ1 elephant" σ),
Undesirable instabilities (with respect to swell 11m' and/or time) result and the former monochrome oxide-silicon boundary [t11
Also, if an avalanche phenomenon occurs very close to the avalanche diode, avalanche noise will occur. To overcome this instability and noise, a non-terminating avalanche (
Or Zener) worldly phenomenon? I tried to provide surface joints that are limited to the joint parts.
'-4 bodies have been proposed. For example, US time d) or 42
No. 15806, No. 4127859 吋, etc.)-41091
6qs, No. 4106048, m4.1060.43
吋 and a, 42os7st-e-u technical state l・dog body is also considered as σ)], but t'gara, 1)
14 θ) U.S. time in σ) -4'; )
It may be thought that σ), -'4-, that is, if the doping level is chosen to be less than about 7 volts, "normal σ)" in the eye circuit manufacturing process: IA!
It is actually ideal for continuous use and does not stagnate.

For example, in the device disclosed in U.S. Pat. 7 for the isolation region when the base region σ) doping level is relatively high and the ``collector'' region is approximately 15 microns deep. ．(
The commonly used surface concentration of the boron dopant is approximately 1020 per cubic centimeter (7-1) to limit the avalanche mechanism to the subsurface n+p+ junction described in this U.S. patent. In the U.S. patent, 5 integrated circuits I/Kori-ro-Kami-Kami σ) Collector region separation '14) K A subsurface avalanche junction is provided by diffusing a specific σ) heavily doped (]4) p region at the desired location of the region. A base region is then formed by a conventional diffusion process, with the specific heavily doped p+ region extending from the silicon surface all the way down to the underlying n-1-1 buried layer. Make sure to completely surround the two sides. Then, the n+
Once the emitter region is formed, the aforementioned imitation of U.S. Pat.
and the surface concentration is 10. It has long been known that on the atomic scale, they cause surface damage, including the formation of surface dislocations. Such surface damage and dislocations commonly occur during the subsequent high temperature diffusion "drive-in" step to the p+ isolation region.
and propagates deep into silicon during “emitter” diffusion (1
5) Ro. Because of such defects deep within the silicon crystal structure, the resulting diode will have "leaky" or "soft" junctions that can have a detrimental effect on circuit operation. The surface concentration of the Up+r isolation region for a somewhat lightly doped base region can be made somewhat lower (and still limit the avalanche phenomenon to the subsurface region, but even in this case the p+ boron diffusion The compromise between the deleterious effects of the surface damage caused and the stability and quality of the subsurface diode is quite difficult to gauge.

In addition to the marginal quality of subsurface avalanche diode devices that can be obtained using the structure and method disclosed in U.S. Pat.
Both the "sidewall" capacitance associated with the portion of the p+ region extending from the bottom of the base region of the subsurface diode to the n+ "buried layer" and the capacitance at the junction between the bottom of the p+ region and the top of the n+ buried layer are very large. The disadvantage is that it is expensive. These two parasitic capacitances are parallel to, and therefore add to, the junction capacitance of the subsurface avalanche n+p+ junction between the bottom of the n+ emitter diffusion region and the top of the p+ diffusion region (16).

This total parasitic capacitance is greater than twice the junction capacitance of the avalanche junction itself.

Although the total capacitance associated with an avalanche junction is not important in some applications where the avalanche junction is used as a voltage reference within an integrated circuit, this parasitic capacitance may be significant in other applications. is very important.For example, there is an ordinary operational amplifier circuit.

Resistive feedback from the output of this operational amplifier to one of its inputs is limited by an avalanche diode connected in parallel with the feedback resistor. Since the other input of the operational amplifier is grounded, the output of the operational amplifier rises linearly until the voltage of the feedback resistor increases to the breakdown point of the avalanche diode. Then the output of the operational amplifier is 7
equal to the balancier voltage. Obviously, the additional parasitic capacitance of the avalanche diode reduces the bandwidth of the device and thus impairs it at high frequencies.

Furthermore, the junctions along the aforementioned sidewalls of the subject p-region and the junctions along the boundary between the p+n-buried layer and the p-region are connected in parallel with the desired low-voltage high-stability avalanche diode. The stability of the desired avalanche diode may be compromised due to some "softness" or leakage in these parasitic junctions caused by propagated silicon defects resulting from damage by heavy p+ boron diffusion. performance and low noise characteristics may be impaired.

In summary, the teachings of U.S. Pat. No. 4,213,806 demonstrate that the disclosed subsurface avalanche diode avoids the problems encountered with typical "surface breakdown" diodes, adds one to the normal integrated circuit manufacturing process, and Even though this is achieved without introducing any cost, the fact is that the overall quality of the subsurface avalanche diode is not good, and furthermore, in normal integrated circuit manufacturing processes, p+ separation” diffusion is “critical” (
18) Relatively little process control is typically required for the separation-diffusion process step, since it is not considered a process step, reducing the overall cost of a typical manufacturing process. are doing. However, U.S. Pat.
6806, the required p+ "separation" diffusion requires very precise control if the desired subsurface avalanche junction is to be obtained. Therefore, there is a "hidden" cost in the form of precise control over previously loosely controlled process steps, which would be common if the structure and method of U.S. Pat. No. 4,216,806 were successfully used. This must be added to the cost of the integrated circuit manufacturing process.

This subsurface avalanche diode structure and manufacturing method, despite the aforementioned drawbacks, is probably the one most commonly used today, simply because no other practical structure has been proposed. For example, U.S. Patent No. 41278
The subsurface avalanche diode structure shown in No. 59 is obtained by subsurface avalanche diode (19) because the p-type side of the avalanche diode is heavily doped and the p+ region formed during the "isolation" diffusion step causes damage. It suffers from exactly the same drawbacks as disclosed in US Pat. No. 4,215,806.

At the end of a typical bipolar integrated circuit fabrication process, a heavy (doped p-shadow region) is ion-implanted, in which the ion implantation energy is applied to the resulting heavy (doped p-shadow region) at the previously formed "emitter" n. It is said that a device has been proposed in which a subsurface avalanche junction structure is provided by placing the device under and in contact with the ten region.However, this method is not practical for several reasons. First, the surface damage caused by implantation and the “amorphousness” in the surface silicon
5 and also a long high temperature annealing step must be performed to "activate" the implanted boron atoms by allowing them to take up replacement sites in the silicon lattice structure. This annealing (20) step essentially drives in the previously formed pn junctions and also reduces the impurity concentration immediately on either side of each pn junction, thereby achieving )
If possible, increase the minimum breakdown voltage. Furthermore, using this technique, major changes to the diffusion process may be required to obtain bipolar transistor characteristics that are sufficiently close to those associated with the original bipolar integrated circuit fabrication process.

As those skilled in the art will readily recognize, arriving at a completely satisfactory bipolar integrated circuit manufacturing process is not a particularly easy matter, and significant changes must be made to it just to be achieved. This is highly undesirable and therefore highly stable subsurface avalanche diode structures and relatively low voltage, low The need for noisy avalanche lt Zener diodes remains unmet.

It is therefore an object of this invention to provide an improved subsurface breakdown diode that is highly compatible with conventional bipolar (21) integrated circuit fabrication methods.

Another object of the invention is to generate an unacceptable amount of subsurface damage and/or dislocations in the silicon of the final integrated circuit during the manufacturing process.

It is an object of the present invention to provide an improved subsurface integrated circuit avalanche or Zener diode with a very low electron avalanche or Zener breakdown chamber [E'&.

Another object of the invention is to provide a p-type substrate, an n-type epitaxial "collector" region, a p+ "isolation" diffusion region, a relatively lightly doped p-type "base" region and a relatively heavily doped n+-type "emitter" region. The objective is to provide the lowest possible electron avalanche or Zener breakdown voltage in subsurface diodes made by conventional bipolar integrated circuit fabrication methods, including the formation of "regions."

Another object of the present invention is that in common bipolar integrated circuit structures, the critical (22) elements of transistors and diodes located elsewhere in the integrated circuit can be removed with very little modification to existing process procedures. It is desirable to find a subsurface avalanche or Zener diode structure and method of fabrication that does not substantially affect its performance.

Another object of the present invention is to provide an integrated circuit subsurface avalanche or Zener diode structure and method of manufacture that has low associated parasitic capacitance and low junction currents.

(Invention σ) Summary) To briefly describe an embodiment of the present invention, the present invention provides a highly stable low voltage integrated circuit subsurface avalanche or Zener diode structure and a method for manufacturing the same. The body includes a lightly doped p-type substrate, a relatively lightly doped n-type layer, and a plurality of deep heavily doped p-type layers extending from the top surface of this to the p-type substrate.
a p-type "base" region disposed on and extending to the top surface of the first of the two n-type regions;

A heavily doped n-1-'emitter' (23) region disposed in and extending to the top surface of the p-type 'base' region, and adjacent below and adjacent to the n-type 'emitter' region. This consists of a heavily doped p-soil subsurface region disposed in a completely delimited p-type "base" region, with an n-1- "emitter" region in the p-soil subsurface region. There is a fully subsurface p-1-n+ junction between t,4, which does not reach the p-type substrate,
, the same extent laterally as the p-soil subsurface area? The portions of the n-type "emitter" region that have a lower net n-type doping level than the surrounding portions of the n-4-(-emitter) regions on both sides of the p-100 junction The majority carrier impurity concentration is significantly higher than the majority gear impurity concentration in the p-type "base" region, so that
In a diode formed by an n-type "emitter" region and a p-type base region, electron avalanche or Zener breakdown is confined to the subsurface p+n junction junction, resulting in noise and 413', pneumatic instability in the diode. can be avoided.

In the described embodiments of the invention, the first opening for defining (24) the lateral extent of the p-type "base" region (and other base regions in the integrated circuit being fabricated) is After forming the overlying oxide layer, a W1 layer of resist is formed on the surface of the integrated circuit, and a second opening is formed therein to define the lateral extent of the subsurface region. Be it. A large amount of p-type ions are implanted into the surface of the 10th type region through the second opening of 1/cyst, with the resist acting as a mask for the ions. Next, the resist is removed.

The silicon surface is exposed through the first opening. A "pre-deposition" layer of p-type ions is formed on the exposed silicon surface by a lighter concentration ion implantation step, with the surrounding oxide layer acting as a mask, or by a conventional diffusion process outside the integrated circuit. A "drive-in" twist step is performed by heating to a first predetermined elevated temperature for a first predetermined period of time to cause the p-type "base" region to diffuse into the first separated n+ bulge region. .

In the described embodiments of the invention, the predetermined first elevated temperature and the first predetermined time period produce predetermined transistor characteristics and/or other device characteristics (e.g. diffused resistor characteristics). was chosen for a given "normal" bipolar integrated circuit manufacturing operation.

"After the drive-in co-diffusion step is performed, the resulting structure has a heavily doped p+ implant region extending from the surface of the integrated circuit into the type 10 isolation region. The p-type region is laterally surrounded and adjoined by a much more lightly doped p-type space region. Since the p-type impurity concentration in the implanted region is much higher), it extends slightly below the bottom of the peripheral part of the p-shadow region.

The integrated circuit is then formed with a second oxide layer, in which a VC fifth opening is formed to define the lateral extent of the n+-type "emitter" region. This sixth aperture delimits and surrounds the p-type implant region. An n+ diffusion step is then performed to form a very heavily doped n+ "emitter" (26) region. Since this R + impurity concentration is considerably higher than the P + impurity concentration in the P + type implanted region, the two-way portion of that region is converted to n + type material.

The lower portion of the p-type implanted region remains n-type and constitutes the aforementioned "n-type subsurface region." Elsewhere in the integrated circuit, the electrical characteristics of IC-formed transistors are largely unaltered by the process changes required to form the P-type subsurface region in the Fi-10 region. n ten form
Since the p+ and n+ impurity concentrations on both sides of the p+n subsurface junction between the emitter region and the n+ subsurface region are very high, a very low electron avalanche (or zener) can be achieved as desired. You can get it.

DESCRIPTION OF THE INVENTION This invention may be best understood by first describing the structure of a completed subsurface avalanche diode with reference to FIG. 1 is a partially perspective cross-sectional view of an integrated circuit structure according to the present invention after completion of the last operation in a manufacturing process; FIG. (27) In FIG. 5, the steps of cutting the oxide opening and providing metallized connections to the anode and cathode of the surface-bottom avalanche diode 20 are omitted for simplicity. Note that These steps are completely conventional in the art of integrated circuit manufacturing and form part of this invention.

In FIG. 5, an integrated circuit structure 10 comprises a lightly doped p-type substrate 5, which is typical of a typical VCR6. It may be approximately 15 mils (3.8 x 10 -2 cnT) thick. A plurality of heavily doped p-type isolation diffusion regions 1 extend from the top surface of the n-type layer B to the p-type substrate 5, with a relatively lightly doped n-type epitaxial layer 6 disposed on the top surface of the substrate 5. Multiple electrically isolated n such as A
It forms a shadow area. (As you should have noticed, in the separate n-shaded regions of Shingaki other than those shown in Fig. 5, vertical n p n transistors, horizontal pn p transistors, and diffused resistors are formed in the mungagami. Such a separate n-shade region will be referred to below as a ``collone (28) region''. However, more often than not, it will be referred to as a ``E emitter'' region. (all of the foregoing structures are quite common in bipolar integrated circuit technology), generally designated 20 in FIG. A subsurface avalanche diode rrin type isolation region 3AK is provided as shown in FIG. The subsurface diode 20 has a p+n+ junction 29, which lies completely below the top surface 6' of the n-type layer 6.9 On-surface avalanche diode 200 The cathode has a heavily doped n+ peripheral region 27 5, which is part of the total n-)-"emitter" region, as will be explained later. Peripheral area 2
A subsurface avalanche diode 20 adjoining and completely surrounding the inner region 27'' of the emitter region 27 at 7' has a heavily doped p-soil subsurface region 19''.
This is included in the P-type ``base'' reconnaissance area, generally indicated by the numeral 18 in Figure 5, and can be thought of as part of this (29). (It should be appreciated that p-shadow region 18 is also formed elsewhere in the integrated circuit structure (during the p-type diffusion step used to form all of the transistor-shaped base regions). Similarly, the n+ region, designated 27, fabricates the n+ emitter of an npn transistor formed elsewhere in the integrated circuit structure. is formed during the same diffusion step as the ``emitter'' region, and is therefore referred to here simply as the ``emitter'' region. Such designation is commonly used by those skilled in the art, so it is easy to use it here. According to the invention, the concentration of n-type impurity carriers in region 27" is typically approximately 10 atoms per cubic centimeter, and the concentration of p+ impurity in region 19" is Typically 101 per cubic centimeter
Although in the range of 9 to 1020 atoms, a typical value in region 19'' is that the electron avalanche or Zener breakdown (30) πThEf of the subsurface vibration region 29 should be about 6.5 volts. is desired.”
Approximately 4 x 101 per 11 cubic centimeters
If the p+ impurity in the region 19 adjacent to the junction 29 is low, the electron avalanche breakdown of the subsurface avalanche diode 20 will increase to 7, which will be 9, a typical integration. In the circuit manufacturing process, the base area IE
L7) The sheet resistance should be within the range of 7 x 1018 to 1 x 1019 per cubic centimeter, respectively.
Depending on the shape impurity degree, it will be 150 to 250 ohms per unit area for a junction depth of about 15 microns. The higher the value of p-type impurity in the base region 18, the lower the electron avalanche or Zener breakdown voltage between the emitter region and the base region. Normally, this emitter-base breakdown voltage would tend to occur at the surface point indicated at 61 and would be susceptible to the instability described above. However, the subsurface p-domain 19
" exists, and the p-type impurity sputum content of this is base region 18
(3) anywhere in the region 19A', the p-1-n+ junction 29IC&
The breakdown electric potential FE at the surface point 51 is considerably lower than at the surface point 51.

As will become more apparent, the fabrication method of the present invention, described below, allows the electronic avalanche breakdown of the subsurface p+n+ junction 29 to be consistent with the characteristics of most common prior art subsurface avalanche or Zener diode structures. For prior art subsurface avalanche diode junctions such as 29' in Figure 6 (without excessive surface damage)
Allowing you to get considerably less than you would actually get.

Before describing in detail the advantages of the subsurface avalanche or single-channel diode structure shown in FIG. It will be useful to understand this in detail.This manufacturing method will now be explained with reference to Figures 1 to 4, and the differences between the manufacturing methods of the present invention and those of the prior art will also be explained. do.

Now looking at Figure 1, the p-sufficiently separated diffusion region 1 has the shape (32) Integrated circuit structure 10 is shown after it has been completed.

The surface impurity once N for the diffusion process of the p-sufficient diffusion part 1
5 is a non-critical parameter in the method of this invention, typically 101 per cubic centimeter everywhere.
In the range of 9 to 1020 atoms. arbitrary deep p+
As in separation diffusion, the concentration of p-type carriers decreases rapidly from its initial surface value N3. As those skilled in the art will appreciate, 2 this surface concentration is non-critical tc.
Being a manufacturing parameter reduces the manufacturing process compared to if Ns were a critical parameter, as required for the aforementioned prior art methods for making subsurface avalanche diodes. In contrast, the corresponding p-sufficient thermal diffusion step required in the aforementioned U.S. Pat. In order to obtain an electron avalanche of electricity as low as 7 volts at a junction such as the n-1-p+ junction 29' of a technical structure, approximately X10 per cubic centimeter is required.
It requires a high surface 6 degree Ns of 20 (33) atoms. As those skilled in the art know, such high surface concentrations for boron diffusion (used to form isolation and base regions in most conventional integrated circuit fabrication methods) This creates a serious surface "pitting" problem that has plagued the integrated circuit industry for many years. The above-mentioned high surface for p-sufficient diffusion is also used in the prior art structure of FIG.
induces significant dislocations in silicon. Separation area 1
During the next drive-in step in which K' is diffused through the n-shaded region to the p-substrate, this dislocation propagates into the n-shaded region 3A, resulting in the ultimately formed diode junction 29' of FIG. 55 and 67 will have very undesirable leakage currents that are highly temperature dependent and ultimately cause undesired drift l' in the electrical characteristics of the formed subsurface avalanche junction diode. Therefore, the level of surface damage is high (and therefore has a breakdown (34) voltage much lower than about 7 volts due to low yield and high instability). It is rather undesirable to use diagram structures.

Returning to FIG. 1 again, after the isolation diffusion part 1 is formed, an opening 7 is made in the silicon dioxide layer 9 formed on the second surface 6' of the Jdn type epitaxial layer 5 according to the manufacturing method of the present invention. , the opening 7 of the integrated structure includes the step of defining the lateral extent of the "base" region 1B (FIG. 5) by exposing the region 16' of the collector region 3' of the collector region A. The base opening (not shown) is formed at the same time as the "base opening" (not shown) is formed for the transistor.

Referring now to FIG. 2, the next step in the method of the invention is to cover the entire top surface of integrated circuit structure 10 with a typical layer 11 of photoresist (which may be about 1 micron thick). The idea is to attach it and make it function as an ion implantation mask. Next, create an opening 15 in the photoresist layer 11 at the center position within the base opening 17 to expose the surface (35) region 1677. 2, a p-domain 18 is implanted into the surface 15' through the opening 15, as shown by the arrow 17, which represents the bombardment 7 of the entire top surface with boron atoms, which results in the bombardment 7 shown in FIG. A p+ region designated by the reference numeral 19 is formed.In the previously described configuration example of the present invention, an electron avalanche breakdown voltage of about 6.5 volts is generated at the ultimately formed subsurface avalanche junction 29 (FIG. 5). In this case, the region 190
Surface concentration is approximately 4 x 101 per cubic centimeter
It has 9 atoms. The ion energy used (1 approx. 50
keV. However, the impurity concentration in region 19 is between 1×10 and I×1 per cubic centimeter.
This can be achieved by keeping it within the range of 020 atoms.

Referring now to FIG. 5, the next step in the fabrication process is to remove the photoresist layer 11Y and extrude the entire surface area 15 through the oxide opening 7. Surface area 15' also remains thermally exposed. Next, as indicated by the arrow 21, the collection port (36) channel structure 10 is again bombarded with boron ions, and the p shadow region 19A is implanted into the feeding portion of the surface 1 surrounding the p+ region 19. . The surface concentration of region 19A depends on the desired resistivity or sheet resistance of the base region of the vertical npn transistor being formed elsewhere in the integrated circuit, but is typically about 7 x 10 per cubic centimeter.
It can vary between 1 and 1019 atoms.

This ion bombardment somewhat increases the p-type impurity level in region 1di9A, but is almost relative to the already very high doping level in region 19:
(I want to make an impact.

Referring now to FIG. 4, the next step in the manufacturing method of the present invention is to heat the integrated circuit structure 10 at a high temperature (typically 1100 degrees Celsius) for a sufficiently long period of time (typically i
']d2 time) to "drive in" areas 19 and 19Ay, thereby creating relatively deep areas 19' and 19A'4 as shown in FIG. At the same time as region 19A' is formed.

Elsewhere in this integrated circuit structure, vertical blades (37
) direction n p n ) The base region of the transistor is also formed.

The depth of region 198' is approximately 2.5 microns in the described embodiment of the invention.Referring now to FIG. Thermal oxide layer 2
6, etching an "emitter opening" 25 therein and diffusing into the n+ "emitter" region 27. Oxide opening 25 completely surrounds and is separated from the intersection 35 of region 19' and top surface 6'; therefore, emitter region 27 has peripheral portion 27 having a surface concentration of approximately 1020 atoms per cubic centimeter.
' and an inner portion 27'' having a somewhat lower "net" n-type impurity concentration, in which the p-type impurity concentration is initially lower than in the remainder of the base region 18. The impurity concentration was much higher than that in the n+jJt region 27 in Figure 5.
The low impurity concentration in the substrate may typically be on the order of 7.times.10@19 atoms per cubic centimeter.

(38) With the foregoing background, those skilled in the art will readily recognize - ``In spite of the fact that in the foregoing manufacturing method.

The amount of time that the integrated circuit 111f structure 10, in which the p10 regions 19' are formed, is exposed to high temperature is extremely inconceivable. For this reason, the emitter region 2
Most of the p-type impurity in region 19' is caused by the emitter diffusion forming 7? This is because it does not require a sufficiently high temperature for a sufficiently long period of time to diffuse considerably deep into the n-shaded region 6A toward the substrate 5.

However, in contrast to f, t-, conventional fabrication methods use sufficiently low surface impurity concentrations to form the p+ isolation region 1' (FIG. 6). Severe surface damage, pitting, etc. and silicone (
If you try to avoid dislocation formation, the region 1'
Since the diffusion distribution of the subsurface avalanche diode 20 (FIG. 5) of the present invention suddenly decreases, the p+ impurity concentration along the subsurface graded portion 29' (FIG. 6) of the prior art is lower than that of the subsurface graded portion 20 of the present invention (FIG. 5). It is unlikely that the price will be significantly lower than that on 29th (39th). It may therefore be appreciated that the above-described method essentially allows for the creation of more stable and lower voltage subsurface avalanche or energized diodes than previously possible.

As the technically savvy would now well know,
In order to control the breakdown voltage EY of the subsurface avalanche diode of the prior art structure shown in FIG.
Although it is necessary to very closely control the diffusion process parameters of the filter insert used to form the
This adds cost and inconvenience to manufacturing process steps that are normally considered non-critical.

Let us now discuss another significant drawback of the prior art structure shown in Chain 6. As can be seen from a close look at FIG. 6, the subsurface n-1-p+ junction 29' originally has a "side wall" junction region, designated by the reference numeral 65, which constitutes the p+n+ junction, parallel to it. In FIG. 6, there is a p-1-n+ junction region indicated by a dot 7. Those skilled in the art will appreciate that in order to prevent the anode (40) of the subsurface diode shown in Figure 6 from shorting to the p-type substrate, an n+ buried layer 59 is formed in the substrate. These additional p-n junctions form two parallel (C-connected) subsurface diodes with the desired low voltage subsurface avalanche junction 29'. Their junction capacitance is , whose sum is greater than twice the junction capacitance of junction 29', significantly increasing the total capacitance of the resulting avalanche diode.

Furthermore, all leakage currents associated with these parasitic junctions 1d add to the leakage current of junction 29'. As previously mentioned, this high capacitance may be highly undesirable in certain applications that require a precise, stable, low voltage avalanche reference diode. 6th
Any additional leakage current added to the leakage current of the subsurface junction 29' in the prior art device of the figure is very temperature dependent and also increases the instability of the subsurface diode. It is undesirable. Furthermore.

As you should have noticed, it is unique to the structure in Figure 6 (4)
The additional parasitic junction region () required to create region 1' by p-diffusion is due to the detrimental effects of thermally propagated dislocations that initially occur at the silicon surface as a result of the heavy surface doping concentration mentioned above. Increases the likelihood of damage to the avalanche diode.

Not surprisingly, for the typical boron diffusion predeposition step, the initial surface concentration of dopant from the predeposition source must be very high. The actual diffusion distribution of the completed junction is as follows: assuming that the p-doped impurity concentration in the isolation region is at the depth of the emitter diffusion junction, and that the p-sufficiently separated diffusion region 1' in Figure 6 does not need to be made very deep. It is much lower than that.

The subsurface avalanche diode structure and method of making the structure shown in FIG. 5f) In the centralized circuit structure 10, there are no parasitic junctions (e.g. 55 and 67 in FIG. 6), and the thermal (42) propagation transition ("; the absence of L and the absence of extensive "parasitic" junction areas results in higher yields (and therefore lower production costs) than in prior art structures; , a more leak-tight junction for the reference diode.The structure of the present invention also
Or because there is no need to create the p-well pre-region 1 in a "tightly controlled" diffusion method.

Control of the process steps of this method can be relaxed and its cost reduced. The method for making the structure of FIG. 5 is to anneal out the amorphous silicon produced by the initial implantation of region 19 (FIG. 2) already present in most common bipolar integrated circuit structures. No additional high temperature is required beyond the temperature used, since this annealing occurs automatically during the normal high temperature base and emitter diffusion steps. According to this method, process engineers can adjust the emitter diffusion period slightly to increase the bipolar transistor gain (i.e., as is commonly done).

It is possible to obtain the desired value of "beta") (43
) is easily possible. This process step may require a subsequent high temperature annealing step as in the previously mentioned prior art process step which involves implanting a subsurface p shadow region after the emitter region is formed. It would be very difficult to do so.

Although the present invention has been described in terms of specific configurations thereof, those skilled in the art will be able to make modifications to the disclosed structure and method without departing from the true spirit and scope of the invention. It could be done. Achieves substantially the same effect of obtaining a low surface electron avalanche or Zener breakdown type IE with low parasitic junction capacitance and low parasitic leakage current in substantially the same way without causing excessive surface damage to the semiconductor surface. . Substantially equivalents of all of the described steps and elements of each of the described methods and structures are intended to be included in the present invention. For example, it is not critical that any particular step for providing a doped region consists of an ion implantation step or a convective heat adsorption step. Similarly, the material for the mask can be used as long as it performs the masking function (44). Although a northerly-shaped area is shown for illustration purposes, which will not be needed at all in the mask, one localized area θ) is rounded by areas 19" and 27" to avoid concentration and preferential yield locations. It may be desirable to make it into a shape,

[Brief explanation of drawings]

FIG. 1 is a partial perspective cross-sectional view of the integrated circuit structure after the isolation diffusion has been completed and the oxide openings defining the lateral extents of the base region have been created; FIG. 5 is a partial perspective cross-sectional view illustrating the structure, which is useful for explaining the subsequent process steps in manufacturing the subsurface avalanche diode of the present invention. FIG. Figure 4 is a partial perspective cross-sectional view of the structure shown in the cross-sectional view after subsequent process steps have been performed; (45) FIG. 5 is a partial perspective cross-sectional view illustrating the structure of FIG. 4 after the subsurface avalanche diode of the present invention has been formed. FIG. 6 is a prior art structure. 1 is a partial perspective cross-sectional view of the body, which serves to point out the salient features of the invention. In these figures, 1 is the p-well pre-diffusion region;
1 formed pitaxial layer, 3A is [collector 1 (n type) region, 5 is p type substrate, 7 is base (oxide) opening, 10
11 is an integrated circuit structure, 11 is a photoresist layer, 15 is an opening, 18 is a base 1 (p+) region, 19 is a p+ region,
19A is the p shadow region, 201-j is a subsurface avalanche diode, 25 is the emitter opening, 27 is the 0+ "emitter" region, and 29 is the avalanche junction. Patent applicant: Burr Brown Research Corporation (46)

Claims (1)

[Scope of Claims] (1) a p-type substrate having a first surface; (b) an n-type layer on said first surface and having an outer surface 7; (c) from said outer surface. a p-well front region extending through said n-type layer to said p-type substrate and electrically isolating the tenth type region of said n-type layer from all other parts thereof. d) a p-shaded region located in said tenth-shaped region and whose junction with said n-shaded region ends in said σ) outer plane; (e) a p-shaded region located in said p-shaded region; , the above p
The junction with the shadow region ends at the outer surface, and the heavily doped n+ region (B) is adjacent to and surrounded by the other region (1), and is below the n+iU region (1). ) located adjacent to and together with the subsurface p
a complete subsurface p-region forming a +n region, and the majority carrier impurity 'I's concentration on each side of the subsurface p-1-n junction is as high as the An improved low voltage integrated circuit subsurface avalanche or Zener diode having a p-type impurity concentration significantly higher than any point along the boundary between the p shadow region and the peripheral portion of the n+ region. 2) An annular periphery in which the n-domain extends outwardly beyond all the peripheries of the σ) subsurface p-domain? have. An improved low voltage integrated circuit subsurface avalanche or Zener diode as claimed in claim 1. (3) The improved low current integrated circuit subsurface avalanche or Zener diode of claim 1, wherein the θ) n-type layer has a thickness in the range of about 6 microns to 8 microns. . (2) (・fj front d[σ) entering surface 1ζp+region σ) impurity ge! ■ is lX1019C per cubic centimeter
1 × 1020 atoms + 7) Within the range, 1 layer, 1 cow, 1,? , (,7') written in the range 7th term σ) Improved low 7
F1 integrated circuit subsurface avalanche or tJ Zener diode. (5 less) The impurity concentration (hr + 10 areas θ) is about 1 x 10 atoms per cubic centimeter, "'p
* Scope of request; Qi 4 JfJK description σ) Improved low-market integrated circuit under surface balancier or Zener diode. (6) The above σ) Below the surface 1) Ten oil j area σ) The bottom is i■
Sobapi θ) is placed at a considerable distance θ) from the second part of the n-type layer (・ro, Patent Claim 77/1 (Ha range 5 J: rl t/
C description t7) Improved low market: [f Unbalanced on the surface of the integrated circuit/
A phantom Zener diode. (7) Front i++ wear surface de p4- area and lateral force,
1] Qi%'li o) n 1 [mar] type doping lower than the 4-region 1] Doping region σ) Inner part of the above 1] tI! i-
MQ claim σ) Improved J low flj described in range 5:
IE Collection 11 Summary 1 - Avalanche or Zener diode. (8) Doping level and depth of the p shadow region (3) (1) Part K (v; 7)
) npn) Lancistor σ) base region σ) doping level and depth exactly equal, %, 4y, claim θ) range':
p: 7 JJ'i IC1, e mounting +7) Improved type low%'
Hayabusa private circuit surface doo avalan/engineering Zener diode. (9) The impurity concentration below the human surface in the region sufficiently deep (with the depth of one region being at least 8 microns and being at least 8 microns)
i o 206L low (θ as described in claim 6) Improved low-voltage integrated circuit surface lower avalanche or l.4: Zener diode 00) (a) P-type substrate, crack ) a plurality of regions arranged on the substrate (C part 1 material [1 type region 5 and this 1
] shaped region θ) extending from the outer surface to the above θ) p-type substrate.
IT'' - Nkoo; Then, the above-mentioned outer m1 /7) Dirt 1 o
)Moo)o)-74(BHo)? J: 1. Let me show you part of it. (1)) Qtf ifυ') Masking material on the outside of the first oxide layer (4)! ' + σ) formed by the layer age, and this layer forms the 4th Ml-111-shaped region I,... θ) surface of the 61]
(c) forming the mask material 10) forming the layer 2nd opening 1''part;
) Surface σ) Let's take out the second part, its dice 17) Ri1
The second part σ) boundary is spaced from the first part σ) ta field and is located entirely within this boundary Vl-1-
Rokoto. ((1) Said σ) Through the second opening 11 part Said σ) 10th
The surface of the shaped region θ) sends the Kp type impurity into the exposed second portion to form a shallow heavily doped p+ type first region having the same extent as the second open portion. B) ([゛) Said σ) Skills in removing layers of mask material. (11 Said 17) The first opening is 1lij, and the p-type impurity is added to +'+i+kiθ) 1-) The adjacent shallow 1] type 2 The region is formed, and then σ) the first A++ Mself θ) the first tl or the rl
) 21st area, L is also quite 111 (doped,)
4) Things. (g) n] The above θ) first and (
5) Second area fire 11) Go! : I n Diffuse deeper into the bulge area. (1]) forming a second oxide layer covering the surface portion;
A sixth opening is formed in this second oxide layer to form the first n.
Shape area σ) The sixth part 7 of the surface is exposed, and the boundary of the fifth part is wherever the boundary of the fifth part is θ) 81'! (1) said σ)0'! , 5 through the open holes to form a 11+ region in the exposed portions of the first region and the p-type second region. σ) Has various stages. The inner part where the n ten region of h'lJ extends in almost the same way as the first head region and the Cn 2. ' has a depth smaller than the depth of the first region, the above σ) remains the Ji of the first region (the part is p ten shape θ), and the above σ) ■1+
The area is also the inner boundary Y (!: i The surrounding area that was obtained] shi, the old four σ) IT + region θ) the σ) the 1' top area of the inner part σ) the p(6) + bottom part σ) the pfn between them 10 subsurface junctions are formed, and this p + n 10 subsurface junctions σ) are placed on each side of the second region and the peripheral portions of the [1+ region]. σ) is significantly higher than the p-type impurity concentration along the junction, thereby causing the
An improved highly stable, low voltage integrated circuit subsurface avalanche or Zener diode is designed to confine the Ichiko avalanche phenomenon and Zener tunneling phenomenon to the vicinity of the above-mentioned p+n subsurface junction. Production method. 01) The aforementioned σ) masking material is a photoresist material.
The method according to claim 10 (step 121 (
It consists of bombarding fl with the above-mentioned chip keion. A method according to claim 10. 0 moat A base region for an npn transistor is formed in the other electrically isolated n shadow region at the same time as the second region is formed, and a base region for the npn transistor is formed simultaneously with the formation of the n+(7) region. 13. The method of claim 12, further comprising forming an emitter region for a transistor (npn). 04) The p-type ions in step (d) are heated to 60 to 70 kC■
17. The method of claim 16, having an energy in the range of . (151(a) a p-type substrate, a plurality of electrically isolated n-shaded regions disposed on the substrate, and a plurality of p-sufficient M extending from the outer surface of the n-shaded regions to said p-type substrate.
A first opening is formed in the first oxide layer disposed on the outer surface at the surface of the semiconductor chip consisting of a region wi, and the opening 21'l of the surface: (b) forming a layer of masking material on the outer surface of said first oxide layer so that said layer of said first oxide layer is partially exposed; forming a second opening in the layer of masking material to deposit a second portion (8) of the surface of the first n-type region; The boundary of the second part is the same as that of the first part.
Bombard the surface of the chip in item 11 with Kel-shaped ions so that they are spaced apart from the boundary of the part and completely located within this boundary, and some of these ions are implanting a shallow heavily doped p1 first region coextensive with the second aperture by implanting a second exposed portion of the surface of the n shadow region through the second aperture; Formation-1-Rotation. (e) Removing said layer of masking material; (
f) sending a p-type impurity through said first opening to form a shallow p-type impurity surrounding and adjacent said first region;
forming a shaped second region, said first region being significantly more heavily doped than said second region; (gl The above-mentioned chip is underheated and the above-mentioned first and second
(hl Form a second oxide layer covering the surface portion and form a sixth opening in the second oxide layer9) and the fifth portion 7 of the surface of said tenth shaped region is exposed, the boundary of said 2.6 portion being spaced everywhere from and located between the boundaries of said first and second portions; (1) sending an I-type impurity through the second opening to form an n-type region in exposed portions of the first region and the second p-type region; It has several process steps. Is the lateral extent of the n10 region approximately the same as that of the first region? having a depth smaller than the depth of the first region, the bottom portion of the first region remains p-shaped, and the 11+ region also has a depth smaller than the depth of the first region. a peripheral portion with an outer boundary and an inner boundary that is substantially liquid at the junction between said bottom portions of one region;
σ) inner part of the n0 region and the (7J'
:1 area σ) The above p+ bottom part is p+n between the two.
A subsurface junction is formed in the subsurface junction, and on each side of the p -1 -n subsurface junction, the majority carrier impurity concentration is between the second region and the periphery of the n region. Part (10) Part θ) σ) Junction ((bath θ) ■) Type impurity concentration L
1"t yo C commonly, j+'j, < 1: c is O, ;su, towa W, the above θ) r] ten territory 1 formation, the above θ) 100' 11 and the 2nd territory 1 power The diode formed by σ)7 + notation θ) 1)] -
] 111 surface 1-1'g: 1 part restricted near 17' -4-
4) It was made by a 115-force manufacturer with a high stability and low level integrated circuit surface door balancier (1 Zener diode).