JPS59913B2 - Magnetic bubble storage control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for repairing defective loops in a storage device using a magnetic bubble storage element having a defective loop in a portion thereof.

The operating principle of the magnetic bubble memory element is described, for example, in the "Bubble Technology Handbook" published by the Institute of Electrical Engineers of Japan in 1976.
Since it is a well-known technique and is memorized in detail, it will not be described here.

Magnetic bubble memory elements are mass-produced using advanced microfabrication technology, but there is a certain probability that defective loops will exist on the chip.

Currently, if only chips with no defective loops are treated as non-defective products, the yield will be extremely low, which will hinder the reduction in chip prices. However, if a certain number of defective loops are allowed per chip, a significant improvement in yield can be expected. At this time, the stored information must be stored avoiding defective loops. Two typical methods will be explained. One is a method in which an appropriate number of secondary loops corresponding to a desired yield are provided in advance in a chip, and is called a spare loop method. Another method is to provide an appropriate number of secondary chips when a plurality of chips are operated in parallel, and is called a spare chip method. This is a method in which when a certain minor loop of an information storage chip is a defective loop, a minor loop at the same position on a spare chip is used as a replacement. Normally, the switching operation between the defective loop and the spare loop used in the above two methods is electrically performed outside the chip based on defective loop position information stored in advance in some storage medium. Conventionally, as a storage means for defective loop position information, as disclosed in Japanese Patent Laid-Open No. 52-34639, etc., a read-only storage element in which information is durable is hereinafter abbreviated as ROM.

), the defective loop position information can be stored in a specific loop on a bubble chip, and the defective loop position information can be stored in a specific loop on a bubble chip or used as disclosed in Japanese Patent Laid-Open No. 51-82531. Store it in a place,
There is a device that reads this data after power is turned on and transfers it to a random access memory (hereinafter abbreviated as RAM) before using it. These methods have drawbacks, such as the need for special storage elements such as ROM and RAM, and the need to ensure the defect-free nature of specific loops on the chip in order to store defective loop location information. It was hot. The object of the invention is therefore to avoid the need for special storage elements;
It is an object of the present invention to provide a magnetic bubble storage control system that can be used even if the number of defective minor loops is less than a predetermined number.

In order to achieve the above object, the magnetic bubble storage method according to the present invention provides n
The (n+1)th and (n+1)th (N>n≧1, m0d.N) bubble chips do not have a defective minor loop at the same position, and the binary information represented by the defective minor loop is, for example, “O”.
Then, on a predetermined line that crosses the minor loop of the (n+1)th bubble chip, there is a minor loop corresponding to the position of the defective minor loop of the n-th bubble chip. "O" is stored in the corresponding minor loop, and the information stored in the desired line of the n-th bubble chip and the above 1 of the (n+1)-th bubble chip are stored in the corresponding minor loop.
The defective minor loop position information expressed as ``1'' or ``0'' stored in the line is read out synchronously, and the information on the n-th bubble chip is only when the defective minor loop position information is ``0''. The gist is that it is valid.

In an advantageous embodiment of the present invention, the magnetic bubble storage control device includes means for storing defective minor loop position information of each other bubble chip in one line crossing the minor loop on each bubble chip of the plurality of bubble chips; 2 on the line of normal minor loops located at the same position as the defective minor loops of other bubble chips.
The defective minor loop is detected by storing binary information such as ``1'' on one line of the minor loop at a position that mutually matches the normal minor loop position of other bubble chips. means for configuring position information in binary numbers; means for synchronizing and driving at least a bubble chip with a read/write access request and another bubble chip storing defective minor loop position information of the bubble chip; A control means for reading defective minor loop position information of the bubble chip having a read/write request from other bubble chips in synchronization with read data output from the bubble chip or write data input to the bubble chip, and a bit string of the read/write data. Among them, the information on the bit position corresponding to the defective minor loop position is invalidated in the case of read data, and in the case of write data, binary information that does not cause any inconvenience on the defective minor loop, for example, 2 corresponding to the state where no bubble exists. and a switching operation means for performing an operation of shifting by one bit by inserting advance information based on the defective minor loop position information.

In a further advantageous embodiment of the invention, the switching means includes a first-in-first-out buffer memory and a chip select circuit.

Hereinafter, the present invention will be explained in more detail using examples with reference to the accompanying drawings, but these are merely illustrative.
Of course, various improvements and modifications can be made without going beyond the scope of the present invention.

First, a method for storing defective minor loop position information according to the present invention will be explained using FIG. 1, taking as an example a device consisting of two chips of the same type with a medium-minor loop configuration each having several defective minor loops. . In FIG. 1, A-chip 1 and B-chip 2 are magnetic bubble chips having a major minor loop configuration, and are selected so as not to have defective minor loops at corresponding positions. The structure inside the chip consists of major loops 3 and 4 and a plurality of minor loops. The defective minor loops of chip a are the minor loops 5 and 6 marked with an x, and the defective minor loops of chip a are
It is assumed that the defective minor loop is minor loop 7, which is also marked with an x mark. A bubble row composed of bubbles located at the same position in a plurality of minor loops is herein referred to as a line. The position information of the defective minor loop described above is as follows: In the initial bubble stop state when being accessed as shown in FIG.
The defective minor loop position information AbX of the b chip 2 is stored in the leading line 8 closest to the major loop 4 of the b chip 2, and the defective minor loop position information AbX of the b chip 2 is stored in the leading line 9 closest to the major loop 3 of the a chip 1. do. That is, the defective minor loop position information of each chip is stored in advance in the leading line of the chip. Normally, there are no bubbles in the defective minor loop, and the data of the loop is all 0. Therefore, we decided to store "1" (black circle in Figure 1) only in the first line of the minor loop at the same position as the defective minor loop position of other chips.In this way,
Two chips whose defective minor loop positions do not overlap each other are combined to store defective minor loop position information of the other chip. Next, the defect relief operation based on the present invention will be explained using FIGS. 2 to 6.

FIG. 2 is a block diagram showing the overall configuration of the device. A-chip 1 and b-chip 2 are two sets of direct peripheral circuits 20, each consisting of a coil 1 drive circuit, a chip drive circuit, a sense circuit, etc.
21, respectively. Direct peripheral circuit 20, 2
1 and the switching operation circuit 22 are connected by input/output data lines 23 and 24 that transfer read and write data. Further, the direct peripheral circuits 20 and 21 and the control circuit 25 are connected by control lines 26 and 27. The switching operation circuit 22 and the control circuit 25 are connected by an input/output data line 28. Based on such a circuit configuration, the operation when a read request occurs will be explained in chronological order using FIGS. 3 and 4.

FIG. 3 shows the timing relationship of the control signals corresponding to each of the a-chip 1 and the b-chip 2. In Figure 3, C
start is the coil 1 drive start signal that starts applying the rotating magnetic field for driving the chip, TOut is the transfer out signal that transfers the bubble from the minor loop to the major loop, Det is the bubble detection signal, and Tin is the transfer signal that transfers the bubble from the major loop to the minor loop. signal, C
stOp is a signal for each operation of the coil drive stop signal that stops the application of the rotating magnetic field. Now, when a read request comes to A-chip 1, the coil of A-chip 1 is driven prior to B-chip 2. At time t1 when the line to be read from A-chip 1 reaches the transfer gate position, a transfer-out signal is sent to A-chip 1, and at the same time, a coil, drive start signal and transfer-out signal are sent to d-chip 2 in a superimposed manner. do. As a result, the accessed line containing the read data of the a chip 1 and the defective minor loop position information Bax of the a chip 1 stored in the first line of the b chip 2 are simultaneously sent onto the major loop of each chip. This is led to a detector and read out by each chip. As a result, the readout monitor of the accessed line for which the readout request was made and the corresponding defective nanotop position information are read out in time synchronization, and sent to the switching operation circuit via the input/output lines 23 and 24. Sent to 22nd. After the read operation is completed, both chips perform the transfer operation simultaneously, and the bubble returned to the minor loop receives the coil drive stop signal and stops at times T4 and t5 when it reaches the initial start/stop position of each chip. In this way, one access operation is completed. As explained above, in order to align the timing of the transfer-out operation between both chips and synchronize the read data and defect minor loop position information,
The coil 1 drive start operation is performed by delaying the b-chip 2 by a time (between TO and t1) corresponding to the address of the line requested to be accessed by the a-chip 1. These controls transmit control signals created by the control circuit 25 to the control line 26.
, 27 directly to the peripheral circuits 20, 21. FIG. 4 shows the state of bubble transfer between the a-chip 1 and the b-chip 2 at this time.

As shown in FIG. 1, the defective minor loop position information Bax of the a chip 1 is stored in the first line 8 of the b chip 2, and the defective minor loop position information AbX of the b chip 2 is stored in the first line 9 of the a chip 1. The data B on A-chip 1, for which a read request was made, is on a certain line 60 on A-chip 1.
shall be included in. Figure 4 1,,, are the third
Time point T shown in the figure. , tl, t4, and t5.

The operation of the present invention has been described above in the case where a read request is made to the a chip 1, but the same operation will be performed in the case where a read request is made to the b chip 2, with the a chip 1 and the b chip 2 swapped. . Furthermore, similar control is performed during write operation.

The operation when a write request is made to the b-chip 2 will be described with reference to FIGS. 5 and 6. Similar to FIG. 3, FIG. 5 is a diagram showing the timing relationship of control signals corresponding to the a-chip 1 and the b-chip 2. In Figure 5, Gen
is a bubble generating operation signal for writing write data onto the chip. The difference from the readout operation explained using FIG. write operation. That is, as shown in FIG. 5, it is necessary to perform control so that the timings of the bubble detection operation signal Det of the a-chip 1 and the bubble generation operation signal Gen of the b-chip 2 coincide. To do this, as in the above-mentioned read operation, the timing at which the coil 1 drive start signal for both chips is sent can be changed depending on the address of the line for which the write request has been made. The transfer states of the bubbles 1, . . . in FIG. 6 are at time T shown in FIG. 5, respectively.

,t,,t4,t5. The write data Dw is included in the accessed line 70 to which the write request was made. The above has been explained using an example of the write operation to the b chip 2, but even when a write request is made to the a chip 1, the same control is performed in which the a chip 1 and the b chip 2 are exchanged. Next, an embodiment of the input/output data switching operation accompanying the above read/write operation will be described.

Transfer control of read or write data is executed in the switching operation circuit 22. As an example of this, FIGS. 7 and 8 show a first-in-first-out buffer memory (hereinafter referred to as FIF) in which one word consists of 8 bits.
It is abbreviated as O. ) 80 will now be described. First line 9 of a chip 1 and b chip 2
, 8 store each other's defective minor loop position information AbX and Bax in advance. Both chips are connected to the switching operation circuit 22 via generator circuits 81, 82 and sense circuits 83, 84, respectively. The chip select signal CS sent from the control circuit 25 passes through the chip select signal line 85 to the three chip select circuits 86 and 87.
, 88. Chip select circuits 86 and 87 select chips to input and output write data and read data, respectively. In addition, the chip select circuit 88
This selects the chip from which defective minor loop position information is to be read. An identification signal R/W that determines to which control signal input terminal of the FIFO 8O the defective minor loop position information from the chip selected by the chip select circuit 88 should be sent in accordance with the read or write operation is connected to the identification signal line 90. The signal is then input to the identification circuit 89. FIFO8
At the time of write operation, input data from the control circuit 25 is inputted from a group of eight parallel input lines 91, and output data to the chip is outputted from a serial output line 92. During a read operation, input data from the chip is input from the serial input line 93 to the FIFO 8O, and output data to the control circuit 25 is output from a group of eight parallel output lines 94. The switching operation circuit 22 having such a circuit configuration will be described with reference to FIG. 8, which schematically represents the operation of the FIFO 8O.

Here, it is assumed that an access request is generated in the a-chip 1, and that defective minor loop position information Bax of the a-chip 1 is read from the b-chip 2. First, the read operation will be explained. Read data DrO read from the a-chip 1 at an appropriate timing is input to chip select circuits 87 and 88 via a sense circuit 84. a chip 1
The chip select signal CS is set to "1" (High) in order to use the output from the B chip 2 as read data and the output from the B chip 2 as defective minor loop position information of the A chip 1. At this time, the chip select signal CS is set to "1" (High). The read data DrO input to the chip 88 is inhibited by the product logic gate and becomes invalid, but it passes through the chip select circuit 87 and is input to the FIFO 80 through the serial input line 93.On the other hand, the read data from the a chip 1 Corresponds to D, O.b
The defective minor loop position information Bax of the a-chip 1 stored in the chip 2 is read out at the same timing as explained using FIGS. 3 and 4. This defective minor loop position information Bax passes through a sense circuit 83, passes through a chip select circuit 88 according to the selection conditions of a chip select signal CS, and is input to an identification circuit 89 that identifies the operating mode. Now, the identification signal R/W is 61" (High) during the read operation and "O" (LOW) during the write operation. Therefore, the defect minor loop position information Bax of a chip 1 is 611" (High).
is input to the serial input clock terminal 95 of FIFO 8O, which allows data input when is applied. In this way, the read data DrO from the chip input to the FIFO 8O is transferred to the FIFO 8O in the form shown in FIG.
The data is stored in a buffer memory consisting of 8 bits. At this time, if the bit corresponding to the defective minor loop position in the defective minor loop position information Bax input to the FIFO 8O in synchronization with the read data DrO is ``1'', the serial input clock terminal 95 becomes ``0''. Serial input of information on bits corresponding to defective minor loops in the bit string is prohibited.As a result, FIFO8
The data read from the defective minor loop is not input to O and becomes invalid, and the data read from the normal minor loop adjacent to the defective minor loop is input at the next timing. Only the data read from the normal minor loop is stored in FIFO 8O, and when 8 bits are complete, the clock CK is input to the parallel output clock terminal 96.
8-bit data is output from FIFO 8O by l. The 8-bit normal data D, l is input to the control circuit 25 through the parallel output line group 94. Next, a
The operation of the switching operation circuit 22 when writing to the chip 1 will be explained.

Clock CK applied to parallel input clock terminal 97
2, the write data DwO passes from the control circuit 25 through the parallel human power line group 91 and is input to the FIFO 8O.
Then, the serial output of the stored write data DW8 is controlled based on the defective minor loop position information Bax of the A chip 1 read from the B chip 2 and inputted to the serial output clock terminal 98 of the FIFO 8O. That is, as shown in FIG. 8, the output of the write data DwO corresponding to the defective minor loop from the FIFO 8O is prohibited. The write data DwO is sent out from the FIFO 8O at the next timing so that it is stored in the normal minor loop adjacent to the defective minor loop. in this way,
The serial output of FIFO 8O is controlled based on the defective minor loop position information Bax of chip 1, and the position corresponding to the defective minor loop contains binary information that will not cause any inconvenience on the defective minor loop, for example, a data string in which "0" is inserted. Actual write data DW. It is stored in the a chip 1 via the chip select circuit 86 as 1. Above, we have explained the case where there is an access request to a-chip 1.
When an access request is made to the b-chip 2, the chip select signal CS is inverted and the same operation is performed. In the above embodiments, a two-chip device was described. This is a method of mutually storing defective minor loop position information, and has a closed structure with two chips. Therefore, the above embodiment can be applied as is to a device comprising an even number of chips of two or more. On the other hand, for a device consisting of an odd number of chips, a configuration may be considered in which defective minor loop position information is stored cyclically across chips. An example in this case will be described below. 9th
The figure shows a method of storing defective minor loop position information when the device is composed of three chips of the same type, p-chip 200, chip 201, and r-chip 202. That is, p
Chip 200 contains defective minor loop position information P, x, q chip 2 of r chip 202. Previously, defective minor loop position information Q, x of p chip 200, r chip 202 contains defective minor loop position information Rqx of q chip 201. is stored in the first line of the chip. As explained in the embodiment of the device consisting of two chips, when an access request occurs to a certain chip, the chip that stores the defective minor loop position information of that chip is also driven at an appropriate timing, and the read data is Alternatively, the write data and defective minor loop position information are synchronously input to an electrical circuit external to the chip that performs a switching operation, or output from that circuit to the chip. By doing so, the present invention can also be applied to devices comprising an odd number of chips. In general, N (N≧2) with defective minor loops
The present invention can be applied to individual bubble chips.

In this case, if n is an integer from 1 to N, the position information of the defective minor loop of the n-th bubble chip is N
may be stored in the (n+1)th bubble chip with the mode as the mode. In this case, the n-th bubble chip and the (n+1)-th bubble chip must not have a defective minor loop at the same position. In other words, according to the present invention, if N bubble chips are numbered so that bubble chips with numbers adjacent to each other do not have a defective minor loop at the same position, the bubble will be removed no matter where the defective minor loop is located. can be used. As explained above, in the present invention, defect minor loop position information can be obtained on the chip in synchronization with read/write data.
You can store defective minor loop position information. There is an advantage that defect repair can be performed without any need for a special memory element for performing faulting.

Further, the present invention is particularly effective in the case of a device in which the number of chips constituting the device is large, and the number of chips that are simultaneously accessed is half or less of the total number of chips.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a method for storing defective loop position information of two chips according to the present invention, FIG. 2 is a block diagram showing the overall configuration of the apparatus according to the present invention, and FIG. 3 is a timing relationship diagram of control signals during readout. , FIG. 4 is an explanatory diagram of the bubble transfer state during reading, FIG. 5 is a timing relationship diagram of control signals during write, and FIG. 6 is an explanatory diagram of the bubble transfer state during write.
FIG. 7 is a switching operation circuit diagram according to the present invention, FIG. 8 is an explanatory diagram of the operation of the first-in-first-out buffer memory, and FIG. 9 is an explanatory diagram of a method of storing defective loop position information of three chips. 1...a chip, 2...b chip, 3
, 4... Mediya loop, 5, 6, 7...
・Defect minor loop, 8, 9...first line,
22...Switching operation circuit, 23, 24...
- Input/output data line, 25... Control circuit, 26,
27... Control line, 28... Input/output data line, 60, 70... Line, 80...
・FIFOl8l, 82... Generator circuit, 83, 84... Sense circuit, 85...
・Chip select signal line, 86, 87, 88...
・Chip select circuit, 89...Identification circuit, 9
0...Identification signal line, 91...Parallel input line group, 92...Serial output line, 93...
... Serial power line, 94 ... Parallel output line group, 95 ... Serial input clock terminal,
96...Parallel output clock terminal, 97...
...Parallel input clock terminal, 98...
Serial output clock terminal, 200...P chip, 201...Q chip, 202...
r chip.

Claims (1)

[Claims] 1. In a magnetic bubble storage device consisting of N (N≧2) bubble chips having defective minor loops, the nth and (n+1)th (N≧n≧1, mod.N) bubble chips have defective minor loops at the same position. When the binary information represented by the defective minor loop is, for example, "0", one predetermined line that crosses the minor loop of the (n+1)th bubble chip corresponds to the position of the defective minor loop of the nth bubble chip. "1" for the minor loop
, store “0” in the minor loop corresponding to the normal minor loop position of the n-th bubble chip, and store the information stored in the desired line of the n-th bubble chip and the above of the (n+1)-th bubble chip. The defective minor loop position information expressed as "1" or "0" stored in one line is read out in synchronization, and the information of the n-th bubble chip is changed to "0" if the defective minor loop position information is "0".
A magnetic bubble storage control method characterized by being effective only when .