JPS599644U - MOS logic circuit - Google Patents

MOS logic circuit

Info

Publication number
JPS599644U
JPS599644U JP17122082U JP17122082U JPS599644U JP S599644 U JPS599644 U JP S599644U JP 17122082 U JP17122082 U JP 17122082U JP 17122082 U JP17122082 U JP 17122082U JP S599644 U JPS599644 U JP S599644U
Authority
JP
Japan
Prior art keywords
mo3fet
logic circuit
depletion type
mos logic
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17122082U
Other languages
Japanese (ja)
Inventor
穴見　健治
下酉　和博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17122082U priority Critical patent/JPS599644U/en
Publication of JPS599644U publication Critical patent/JPS599644U/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考ｉの第１の実施例を示す回路図、第２図
はこの考案の第２の実施例を示す回路図、第３図はこの
考案の実施例を示す回路図である。 図において、ＱＥｌはエンハンスメント型ＭＯ３ＦＥＴ
、ＱＤＩ、ＱＤ２はデプレッション型ＭＯ３ＦＥＴであ
る。Fig. 1 is a circuit diagram showing a first embodiment of this idea, Fig. 2 is a circuit diagram showing a second embodiment of this idea, and Fig. 3 is a circuit diagram showing an embodiment of this idea. . In the figure, QEl is an enhancement type MO3FET
, QDI, and QD2 are depression type MO3FETs.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デプレッション型ＭＯ３ＦＥＴからなる負荷用トランジ
スタと、該デプレッション型ＭＯ３ＦＥＴと同一極性の
少なくとも一つのエンハンスメント型ＭＯ３ＦＥＴから
なる駆動用トランジスタを具備し、該負荷用ＭＯ３ＦＥ
Ｔのゲートを該負荷用ＭＯ３ＦＥＴのソース又は駆動用
トランジスタのドレインに接続してなるＭＯ３論理回路
において、少なくとも一つのデプレッション型ＭＯ３Ｆ
ＥＴを、上記デプレッション型ＭＯ３ＦＥＴに直列又は
並列に接続し、そのゲートをクロックパルスで制御する
ようにしたことを特徴とするＭＯ８論理回路。A load transistor made of a depletion type MO3FET, and a driving transistor made of at least one enhancement type MO3FET having the same polarity as the depletion type MO3FET,
In an MO3 logic circuit in which the gate of T is connected to the source of the load MO3FET or the drain of the driving transistor, at least one depletion type MO3F
An MO8 logic circuit characterized in that an ET is connected in series or in parallel to the depletion type MO3FET, and its gate is controlled by a clock pulse.
JP17122082U 1982-11-10 1982-11-10 MOS logic circuit Pending JPS599644U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17122082U JPS599644U (en) 1982-11-10 1982-11-10 MOS logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17122082U JPS599644U (en) 1982-11-10 1982-11-10 MOS logic circuit

Publications (1)

Publication Number Publication Date
JPS599644U true JPS599644U (en) 1984-01-21

Family

ID=30373557

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17122082U Pending JPS599644U (en) 1982-11-10 1982-11-10 MOS logic circuit

Country Status (1)

Country Link
JP (1) JPS599644U (en)

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