JPS5996844U - Lead frame for semiconductor devices - Google Patents

Lead frame for semiconductor devices

Info

Publication number
JPS5996844U
JPS5996844U JP19218382U JP19218382U JPS5996844U JP S5996844 U JPS5996844 U JP S5996844U JP 19218382 U JP19218382 U JP 19218382U JP 19218382 U JP19218382 U JP 19218382U JP S5996844 U JPS5996844 U JP S5996844U
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor device
insulating
semiconductor devices
electrode portions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19218382U
Other languages
Japanese (ja)
Inventor
田代　嘉宣
箕輪　文雄
Original Assignee
日本インタ−ナショナル整流器株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本インタ−ナショナル整流器株式会社 filed Critical 日本インタ−ナショナル整流器株式会社
Priority to JP19218382U priority Critical patent/JPS5996844U/en
Publication of JPS5996844U publication Critical patent/JPS5996844U/en
Pending legal-status Critical Current

Links

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第２図は、本考案に係る半導体装置用リードフ
レームの全体を示す平面図および裏面図、第３図、第４
図は、その部分拡大平面図および正面図、第５図ないし
第７図は上記フレーム上の半導体装置用パッケージの形
成過程を示す工程図、第８図は、上記パツをージの斜視
図、第９図は、上記パッケージを用いて半導体装置を組
立てた状態の断面図である。 １・・・リードフレーム、３・・・連結部、４・・・半
導体装置用パツゲージ、５・・・電極部、６・・・接続
部。1 and 2 are a plan view and a back view showing the entire lead frame for a semiconductor device according to the present invention, and FIGS.
5 to 7 are process diagrams showing the process of forming the semiconductor device package on the frame; FIG. 8 is a perspective view of the package; FIG. 9 is a sectional view of a semiconductor device assembled using the above package. DESCRIPTION OF SYMBOLS 1... Lead frame, 3... Connection part, 4... Parts gauge for semiconductor devices, 5... Electrode part, 6... Connection part.

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）平面上に等間隔配置された複数の連結部と、この
連結部間に接続された複数の電極部と、この電極部を互
いに絶縁分離する手段と、この電極部上に一体的に形成
され、かつ前記連結部の長手力向に沿って配置された複
数の半導体装置用パッケージと、この隣接するパッケー
ジ間を擦続する接続部とを有することを特徴とする半導
体装置用リードフレーム。(1) A plurality of connecting portions arranged at equal intervals on a plane, a plurality of electrode portions connected between the connecting portions, a means for insulating and separating the electrode portions from each other, and a device integrally mounted on the electrode portion. A lead frame for a semiconductor device, comprising a plurality of semiconductor device packages formed and arranged along the longitudinal direction of the connecting portion, and a connecting portion that connects the adjacent packages. （２）前記パッケージは、絶縁性樹脂で形成されている
−ことを特徴とする実用新案登録請求の範囲第１項記載
の半導体装置用リードフレーム。(2) The lead frame for a semiconductor device according to claim 1, wherein the package is made of an insulating resin. （３）前記絶縁性樹脂は、ポリイミド系樹脂であること
を特−徴とする実用新案登録請求の範囲第１項記載の半
導体装置用リードフレーム。＝（４）前記電極部を互い
に絶縁分離する手段は、化学エッチング法等によって形
成したスリットであることを特徴生する実用新案登録請
求の範囲第１項ないし第４項記載の半導体装置用リード
フレーム。(3) The lead frame for a semiconductor device according to claim 1, wherein the insulating resin is a polyimide resin. =(4) The lead frame for a semiconductor device according to any of claims 1 to 4, wherein the means for insulating and separating the electrode portions from each other is a slit formed by a chemical etching method or the like. .
JP19218382U 1982-12-21 1982-12-21 Lead frame for semiconductor devices Pending JPS5996844U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19218382U JPS5996844U (en) 1982-12-21 1982-12-21 Lead frame for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19218382U JPS5996844U (en) 1982-12-21 1982-12-21 Lead frame for semiconductor devices

Publications (1)

Publication Number Publication Date
JPS5996844U true JPS5996844U (en) 1984-06-30

Family

ID=30413657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19218382U Pending JPS5996844U (en) 1982-12-21 1982-12-21 Lead frame for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS5996844U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251486A (en) * 1998-02-27 1999-09-17 Origin Electric Co Ltd Method for manufacturing surface-mounted semiconductor device and semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57177548A (en) * 1981-04-06 1982-11-01 Int Rectifier Corp Module for semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57177548A (en) * 1981-04-06 1982-11-01 Int Rectifier Corp Module for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251486A (en) * 1998-02-27 1999-09-17 Origin Electric Co Ltd Method for manufacturing surface-mounted semiconductor device and semiconductor device

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