JPS5997220A - Voltage comparing circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption and attain high sensitivity and shorten a reset time, by connecting two FFs, each of which consists of two MOS transistors (TRs) of the same conduction type, different in polarity each other by MOS TRs to make the circuit constitution symmetrical. CONSTITUTION:The first FF is constituted with n-channel MOS TRs T1 and T2, and n-channel MOS TRs T3 and T4 are connected in parallel to TRs T1 and T2. The second FF is constituted with n-channel MOS TRs T5 and T6, and p-channel MOS TRs T7 and T8 are connected in parallel to TRs T5 and T6. Drain electrodes of TRs T1 and T2 and drain electrodes of TRs T5 and T6 are connected by n-channel TRs T9 and T10. Gate electrodes of TR T7-T10 are connected to a pulse generating source, and voltages to be compared are applied to gate electrodes 202 and 203 of TRs T3 and T4.

Description

Detailed Description of the Invention The present invention is mainly used in an A/D converter etc. realized on a semiconductor integrated circuit with a complementary insulated gate configuration, and compares two voltages with a small difference and calculates the voltage according to the magnitude of the difference. The present invention relates to a voltage comparison circuit suitable for outputting a logic voltage.

Conventionally, as shown in FIG. 1, a voltage comparator circuit used in a semiconductor integrated circuit having a complementary insulated gate configuration uses M1 as a constant current source, M2. M3 is an input transistor, M4.
Differential amplifier 10 configured with M5 as a current mirror type load
As a result, an output voltage proportional to the difference between the voltages applied to terminals 2 and 31 is extracted from terminal 6, and this is further amplified by an inverting amplifier 11 with M6 as a constant current load. was.

The symbols used in this book s1, including Figure 1, are n
The channel transistor is defined as shown in FIG. 2 (al), and the p-channel transistor is defined as shown in FIG. 2 (bl).

In both cases, G indicates the gate, S indicates the source, and D
This is the drain. According to this two-stage amplifier circuit, a gain of 2,000 to 5,000 times can normally be obtained, but in order to obtain margin for gain, an additional transistor M is usually used.
8. One stage of the inverting amplifier 12 consisting of M9 is provided. 13 is a bias voltage supply circuit for operating M1 and M6 in a constant current region.

In such a voltage comparator circuit, when the input voltage decreases, the number of amplification stages must be increased accordingly, which takes up space in the integrated circuit.
This results in an increase in product and power consumption.

Furthermore, the in-phase 'Narita' rejection of the first-stage differential amplifier is not perfect, and when the in-phase component of the input voltage changes, the output voltage at node 6 changes, and this voltage is amplified by the inverting amplifier, so the input voltage In the case of a voltage difference of 1 mV or less, depending on the common mode voltage, the state of logic It I I+ and the state of logic 1IOW may be switched at the output of the final stage.

The same phenomenon also occurs when the power supply voltage fluctuates.

Therefore, in such a voltage comparator circuit, if the common mode voltage of the input voltage changes greatly or if there is a lot of noise in the power supply,
It is difficult to compare voltages below mV. Furthermore, most importantly, the operating center voltage of the differential amplifier 10,
It is very difficult to match the operating center voltages of the inverting amplifier 11, and with current technology, it is common for them to deviate by several hundred mV, resulting in an input offset voltage of around 101 nV. This cannot be controlled with current technology.

Therefore, when comparing voltages, it is necessary to compare voltages that include offsets, and there is a drawback that comparisons using true voltage differences cannot be performed.

Another voltage comparison method is the circuit shown in FIG. 3, which was published by Dingwall in 1979 as 18SCC+c. ('79 l5SCC[)igest
0f Technical papers pp 126
) The details of the operation of this circuit are described in the above-mentioned document and will be omitted here. In this circuit, input voltages from terminals 102 and 103 in the figure are applied to transistors M10. Mll or M12
．． It is connected to one electrode of a capacitor C1 through alternately conductive switches consisting of M13, the other electrode of which is connected to the input terminal of an inverting amplifier constituted by transistors M14 and M2S. The input terminal and output terminal of this inverting amplifier are made conductive in synchronization with the switch.
It is designed to be non-conductive. In the figure, φ and φ are complementary to each other and are locked. For example, when the switch connected to the input terminal 103 is conductive, the input terminal 105 of the inverting amplifier
and the output terminal 106, the transistor M16.
The switch consisting of M+7 also passes through N7, and terminals 105 and 10
Let the potentials of 6 be equal potentials. Next, when the switch connected to the input terminal 102 side is made conductive and the other two switches are made non-conductive, the potential at the terminal 104 changes by the difference between the direct voltage at the terminal 102 and the voltage at the terminal 103. This change is C1
This change is transmitted to the inverting amplifier through the inverting amplifier, and this change is amplified several tens of times and output as an output 106. Therefore, the voltage difference between terminals 102 and 103 is amplified.

Although this circuit may seem simple, the dimensions of the capacitor C1 must be several times larger than the dimensions of the inverting amplifier. Also, the gain of the inverting amplifier is several tens of times at most, and the input voltage difference When the output voltage Fi becomes 1 mV or less, the voltage is not sufficient to operate the logic circuit, so the latch 107
However, considerable amplification is required. Further, since the time at which the voltage at the terminal 103 is sampled and the time at which the voltage at the terminal 102 is sampled are different, if the power supply voltage fluctuates between these two times, that voltage is also treated as the signal input voltage. Therefore, it has the disadvantage of being very weak against power supply noise.

The present invention aims to eliminate such drawbacks and realize a voltage comparator circuit with very high sensitivity using a small number of elements.

The present invention provides a first seven-layer transistor configured by a pair of cross-coupled Hitotsubashi type first and second field effect transistors.
A first 7-channel flip-flop with a common source and drain with the transistor constituting this flip-flop.
The lip-flop is composed of third and fourth field-effect transistors of the same polarity, and a pair of cross-coupled fifth and sixth field-effect transistors of opposite polarity from the first 7-lip 70-tube. a second flip-flop;
A fifth and a sixth transistor constituting a second flip-flop, ninth and tenth field effect transistors having the same polarity as the second flip-flop, whose source and drain electrodes are connected to each other, and a means for generating a pulse. the gate electrodes of the seventh, eighth, ninth and tenth transistors are connected to the pulse generating means, the gate electrodes of the third and fourth transistors are signal hexagonal terminals, and the ninth and a voltage comparator circuit in which the drain electrode of the tenth transistor is used as the output terminal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments. FIG. 4 is a circuit diagram showing one embodiment of the present invention. This circuit is an n-channel MOS) transistor TI,
A flip-flop composed of a plurality of flip-flops T2, n-channel MOS transistors T3 and T4 connected in parallel to each transistor, and a flip-flop composed of n-channel MOS transistors T5 and T6; n-channel MOS) transistors T7. Between the drain electrodes of T8, TI, and T2 and the drain electrodes of T5 and T6 is an n-channel transistor T9. It is guaranteed that they are connected by TIO. And T7. T8. T9. T
The gate electrode of the IO is connected as a terminal 208 to a pulse generation source. The voltage to be compared is T3. Applied to the gate electrodes 202 and 203 of T4. Further, in this circuit, the positive power supply VDD is connected to the terminal 201, and the terminal 209 is grounded. .

This circuit initially starts with a pulse voltage of zero.

When the power supply voltage is 5V and the threshold voltage of the n-channel transistor is O, SV, the input voltage is preferably T.
3. What is the threshold voltage of T4? The circuit can operate at the highest speed if the IV is as high as possible.

This condition will be explained below. T3. Since T4 is conducting, the voltage at nodes 204 and 205 is zero and T9. TIO is non-conducting, T7. Since T8 is conductive, terminals 206 and 207
The potential is equal to the voltage VDD of the power supply terminal 201. Next, when a positive pulse is applied to the terminal 208, T 9 , T
1.0 is exclusive, T7. T8 becomes non-conductive, and T9. T
Current flows into the seven lip-flops TI and T2 through IO. If the potential of terminal 202 is higher than 203 at this time, the current flowing through transistor T3 is greater than the current flowing through transistor T4. No current flows through Tl and T2 until the potential at node 205 or 204 exceeds the threshold voltage, respectively. T9. Initially, when TIO becomes conductive, nodes 204 and 205 are charged in the same way, but node 20
Since node 4 has a larger amount of discharge, node -205 exceeds the threshold voltage first. Then, T1 also starts discharging, and the potential at node 204 does not rise. Therefore, the potential at node 205 continues to rise. Therefore, the current flowing through T9 becomes larger than the current flowing through TIO. Then, terminal 206
Since the potential of T5 causes more discharge than the potential of 207. T6
The flip-flop formed by 206 also operates, and the potential at terminal 206 rapidly drops. In this way, the state of the output voltage is determined according to the input voltage. Since its operation consists of a double 7-lip-flop, the time required for the state to be determined is MOS with a channel length of about 6 microns.
Even if a transistor is used, the speed can be increased to 20 nS or less. Furthermore, since the arrangement is completely symmetrical from input to output, the cause of offset voltage, which is a drawback in conventional circuits, can be eliminated. Further, since the voltage 02 noise is applied equally to both input voltages, it is canceled and there is no risk of malfunction due to the noise. Further, since positive feedback is applied by the flip-flop, the gain is infinite, and even if the input voltage becomes 1 mV or less, a voltage output sufficient for the logic amplitude can be obtained as an output.

Returning to the initial state returns the pulse to zero.

Then T9. TIO becomes non-conductive and T7. T8 is conductive. Then, the charges at nodes 204 and 205 are respectively T3
and T4, while the node 206
, 207 are rapidly charged through T7 and T8, respectively, and return to the power supply voltage "DD." With the circuit configuration of the present invention, this return time can easily be 1 On8 or less.

This circuit does not consume current in its initial state.

Further, even during the comparison operation, only a very small amount of current is consumed, and the power consumption is less than 1/10 of that of the conventional circuit.

The present invention (in the above-mentioned case, the best performance is achieved when the input voltage is higher than the threshold voltage of 'r3.T4 by around IV). An example of this is shown in Figure 5. In Figure 5, a conventional differential amplifier circuit A is added to the circuit B according to the present invention.

[Brief explanation of the drawing]

FIG. 1 shows a conventional differential amplifier 10 and an inverting amplifier 1.
A diagram showing a comparator circuit combining 1.12. Figure 2 (a) shows an n-channel transistor, and the middle part shows a p-channel transistor. FIG. 3 is a diagram showing another conventional converter using an inverting amplifier and a transfer gate as a switch. FIG. 4 is a diagram showing a basic circuit of an embodiment of the present invention. FIG. 5 is a diagram showing an example of a circuit in which a differential amplifier is combined with the present invention to expand the input voltage range. M1-M17. T1~TIO...MOS) transistor. Roku 1 Seki No. 4 Figure 20 Pup No. 5 En A --B

Claims (1)

[Claims] a first 7 flip-flop constituted by a pair of cross-coupled first and second field effect transistors of one conductivity type; first and second transistors constituting this flip-flop; and a source; and third and fourth field effect transistors having common drains and having the same polarity as the first flip-flop, and a pair of cross-coupled fifth and sixth field effect transistors having a different polarity from the first flip-flop. A second 7-lip flop constituted by an effect transistor, and a fifth and a sixth transistor constituting the second 7-lip flop have a common source and drain and have the same polarity as the second 7-lip flop. 8 field-effect transistors, and a ninth flip-flop having the same polarity as the first flip-flop 70-tube, with the drain electrode pair of the first 7-lip flop 70-tube and the drain electrode pair of the second 7-lip-flop serving as source electrodes and drain electrodes, respectively. a tenth field effect transistor and a means for generating a pulse, gate electrodes of the seventh, eighth, ninth and tenth transistors are connected to the means for generating a pulse; A voltage comparison circuit characterized in that the gate electrode of the fourth transistor is used as a signal input terminal, and the drain electrodes of the ninth and tenth transistors are used as output terminals.