JPS5998559A - Field effect transistor - Google Patents

Abstract

PURPOSE:To enable to operate a field effect transistor at a high speed by forming a source and a drain of Ga1-XAlXAs. CONSTITUTION:An i-GaAs layer 11 is formed as a buffer layer on a semi-insulating GaAs substrate 10, and an active layer N type GaAs layer 12, electrode layer N<+> type Ga0.7Al0.7As layer 13, 18, and a contacting layer N<+>-GaAs layer 14 are sequentially grown thereon. An AuGe/Au film 15 is deposited as current injecting contact to drain and source on the obtained wafer, and an alloying heat treatment is performed to ohmically contact the layer 14. A gate part is ethced at the layers 13, 18 through a hole formed at an SiO2 film 16. The etching is stopped at the boundary surface between the layer 12 and the layers 13, 18. Accordingly, the channel thickness tG' directly under a gate electrode 17 is just equal to the thickness of the layer 12. A Schottky gate electrode 17 is formed by aluminum depositing and lifting technique.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to field effect transistors, and in particular to transconductance. The present invention relates to a Schottky barrier gate field effect transistor made of gallium arsenide that has a high m and is capable of high-speed operation.

Structure of conventional example and its problems Field effect transistor made of gallium arsenide (hereinafter referred to as Ga
AsF ICT) is attracting attention as an FET that has superior high frequency characteristics compared to conventional FETs made of silicon. Among them, GaAs2., -]-Mariov Schottky barrier gate FET (hereinafter referred to as normally-off GaAs MICS FET) is excellent in both high speed and low power consumption, and is widely used in logic ICs, memories, etc. Research is underway in various applied fields.

The structure of a conventional Gaps MESFICT is shown in FIG. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a buffer layer, 3 is an active layer, 4 is a drain electrode, 6 is a gate electrode, 6 is a 5102 isolation layer, and 7 is a source electrode. The presence of the series resistance Rs between the gate 5 and the source 7 increases the FIT channel conductance h'' ++Rs,
.

In the conventional GaAs MKSFKT, as shown in Figure 1, an attempt is made to reduce the series resistance Rs by using a recessed structure in which the GaAs layer is thinned just below the gate, but with this structure, the active layer GaAsf must be etched, and the channel thickness is reduced. It is difficult to control satG. The characteristics of normally on, normally 37, and geo-off are determined by the channel thickness tG. For example, if the impurity concentration of n-type GaAs in the active layer is 1 x 1017cIIL-3, the channel thickness tG is 8oO, and the normally-off characteristics are different. , 900
However, with this recess structure, it was not possible to obtain normally-off characteristics with good reproducibility due to the process.Objective of the Invention The present invention realizes normally-off characteristics with good reproducibility and
The source-to-source series resistance Rs is almost zero, so the mutual conductance h is high and G enables high-speed operation.
The entire purpose is to provide aAs MESFET f.

Structure of the Invention The field effect transistor of the present invention is a Schottky pariah gate type field effect transistor in which the active layer is made of gallium arsenide, and the source electrode and the drain electrode are made of gallium aluminum arsenide (Ga, klxAs; O).
<χ≦1).

DESCRIPTION OF EMBODIMENTS The field effect transistor of the present invention will be described below based on embodiments.

FIG. 2 shows a cross-sectional view of the GaAs MES FET of this example, and FIG. 3 shows a plan view of its pattern.

1-G as a buffer layer on a semi-insulating GaAs substrate 1o
An aAs layer 11 with a thickness of 1°0 μm is provided thereon with an active layer of n-GaAs 12'z800 layers and an electrode layer n+-4ao.
,,A,do,3As 13,18i200OA contact layer ri+-GaAs layer 14 is grown 200^, respectively. For growth, the MBE method, uocvn method, etc., which can easily control the film thickness, are used, and in this example, the MBE method was used. The substrate temperature is 7o○°C, the Ga cell temperature is 1100°C, the molecular temperature is 1150°C, the As cell temperature is 250°C, Sn is used as the n-type impurity, and the cell temperature is 780°C.
And so. 1-GaAs layer 11, n-GaAs layer 12, n
-Gao, y Alo, 3AS layer 13°18, n+G
The growth times for each layer of the aAs layer 14 were 35 minutes, 2 minutes 50 seconds, 5 minutes 30 seconds, and 7 minutes 10 seconds, respectively.

The obtained sea urchin...- has a current of 61 to the drain and source.
- A MuGe/MuU film 15 is deposited as a contact for di-implantation, and alloying heat treatment is performed to establish ohmic contact with the contact layer n+-GaSS layer 14. The gate part is SiO
□Membrane 16 Electrode mGa, , Mu8 is passed through the membrane-shaped aperture.
Perform etching steps 13 and 18.

An I2/KI aqueous solution was used as the etching solution.

With this etching solution, GaAS and Gao, 5 ml O
Since selective etching is possible for the active layer GaAs 12 and the electrode layer GaAs 10.
It stops at the interface of 3mm S13°18. Therefore, the channel thickness tG' directly under the gate electrode 17 is just n-G
It is equal to the film thickness of aAs12. Since crystal growth is performed by MBK growth, which has excellent in-plane film thickness uniformity and controllability, tG' = 800X is always formed anywhere on Ueno 1-, and therefore normally-off with excellent reproducibility. characteristics are obtained. The Schottky gate electrode 17 is
Formed by vapor deposition and lift-off techniques.

In the above manner, the MKSFET shown in FIG. 2 is obtained.

In this example, the impurity concentration V of each layer is 1×10 The contact layer 14 is 1×10.

Ga o, y person l, 3As electrode layer 13 is 1X 1Q"
The resistivity is as low as 3 x 10-4Ω, so the resistance between the gate and source is Gao.
,, only the resistance of the active layer n-GaAs layer 12 at a distance of l caused by the side etching of the 5As layer 13 and 18 is reduced, and the electric field of the conventional structure shown in FIG. This is a two-digit improvement compared to the 2000 effect transistor.

As a static characteristic of this MESFET, the threshold voltage vTo, 1
V, (drain current 20 μm), conductance h was 150 m5/parallel, on-resistance was 1500, and propagation delay time was 20 pS, resulting in an element 10 times faster than conventional devices.

vL Furthermore, the Ga as the source electrode and the drain electrode mentioned in the above clarification, the Mu4MuS layer has a Mu1 composition ratio i 0.3
However, the whole range of 0<χ≦1 is applicable. Furthermore, the channel type of the FIT is not limited to n-channel.

7. The digate electrode is not limited to mulch, and any material such as Or-Pt or W-silicide can be used.

Effects of the invention As mentioned above, as in the present invention, "+ -xAlx
By using Sk as the source and drain electrodes, it has become possible to obtain a normally-off field effect transistor with high mutual conductance ym' and high speed operation with good reproducibility.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional field effect transistor, FIG. 2 is a sectional view of a field effect transistor according to an embodiment of the present invention,
FIG. 3 is a pattern diagram thereof. 010...Semi-insulating GaAs substrate, 11...Buffer layer 1-G
aAs, 12--=active layer n-Gamus S, 13...
...Drain electrode layer"-GaO, 7A &, 3 people S114
...Contact layer n+-GaAs, 15...
...mu (Be/Au metal, 16...5i
02.17...Gate electrode, 18...
Source electrode layer n”Ga,, klo,, As. Name of agent: Patent attorney Toshio Nakao and one other person 1st
figure

Claims (1)

[Scope of Claims] A Schottky Variant type field effect transistor in which one power layer is made of gallium arsenide, the source electrode and the drain electrode are made of gallium aluminum arsenide (G
A field effect transistor characterized in that it consists of a,, klxAs; O<x≦1).