JPS60102016A - Digital delay circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is directed to a digital circuit that precisely controls the overall delay time and pulse width of a pulse signal generated by a logic IC tester or the like. Regarding delay circuits, especially i
J? This invention relates to a digital delay circuit in which the rising edge and falling edge of a pulse signal can be finely adjusted independently.

[Background of the invention]

For example, when testing a logic IC, the logic IC under test
For this purpose, it is necessary to apply various pulse signals under extremely strict conditions than the test equipment. FIG. 1 shows the general configuration of a logic IC testing device together with a logic IC to be tested. According to this, a test pattern is given to the IC under test 5 from the gloss turn generator 1 under the control of the main processor 9. The test nozo turn is converted into a pulse signal with a predetermined /e pulse width by the test signal generator 3 according to the generation timing instruction from the timing generator 2, and then is given to the IC under test 5 via the level conversion driver 4. It looks like this. On the other hand, an output corresponding to the test pattern is obtained from the IC under test 5, but after its logic level is determined by the receiver 6, the comparator 7 compares it with the output cover pattern output from the nozo turn generator 1. It has become so. The timing of this comparison is given by timing generator 2, or
If the comparison result from the comparator 7 is defective, various information at that time is stored in the fail memory 8, so that the functions and operating characteristics of the IC 50 under test are tested.

Figure 2 (at, (bl) takes a D-type flip-flop as an example of the IC under test and shows the case where its set time, hold time, and output delay are measured.Input data is detected at the rising edge of the clock. In order for the set time 78ET and the bold time THLD to be reliably set to the flick float 7'lO, the set time 78ET and the bold time THLD must be guaranteed for at least a certain period of time, but the minimum set that can be allowed as the set time Tszt and the bold time THLD f is variable. The purpose is to measure the time and hold time.Also, it is intended to measure the delay time Tpok of the set output or reset output with respect to the rising edge of the clock, but the minimum allowable set time and hold time. In order to measure The pulse width of the pulse signal given to the IC under test and the timing between pulse signals must be controlled with high precision.

However, the accuracy of the pulse signal actually applied to the IC under test from the test equipment usually decreases due to various causes. It is said that the test pulse signal generated by the /e turn generator changes its pulse width and/or the timing between pulse signals before it is applied to the IC under test. It is something.

FIG. 3 shows the driver output when a 4-Noyals signal is applied as input to drivers A and H having the same specifications. As we will see, even if the specifications are the same,
The delay time is TDLE^^~TDLEAo, TDTRAA
The delay time for the rising edge and falling edge is different for drivers A and B, such as ←TDTRAB, and even for the same driver, the delay time for the rising edge and falling edge is TDLEA, A and TDTR.
The difference will be AA%TDLEA m +TDTRA s. That is, the overall delay time and pulse width differ from driver to driver, which causes the timing relationship to deviate from the expected state. In the past, in such cases, the timing relationship was ensured by correcting 10,000 edges on either the rising edge or the falling edge, but this method has also become faster with recent improvements. The reality is that it is unsuitable for other types of ICs. This is because the higher the speed of an IC, the more accurate timing-related tests are required, and for this reason, it is necessary to independently and highly accurately delay control both the rising and falling edges of each pulse signal. is occurring.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital delay circuit in which the rising edge and falling edge of a pulse signal can be independently and highly accurately delayed.

[Summary of the invention]

For this purpose, the present invention arranges two delay elements around the OR element or the AND element.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 4 to 8.

First, the basic configuration of the use of OR elements in the digital delay circuit according to the present invention will be explained with reference to FIG. 4 (at, fbl).

FIG. 4 (al, (bl) shows its configuration and main part input/output signal waveforms, and the input pulse signal IN is processed by the logical OR The output is output from the ORDART element 13 as an output OUT.In this case, the delay time DLI in the delay element 11 is equal to the delay time DL2 in the delay element 12.
Therefore, the main input/output signals become as shown in FIG. 4(b).

As can be seen, the delay time TDLEA of the rising edge of the output OUT is equal to the delay time DLI of the delay element 11.
Furthermore, the falling edge delay time TDTRA is the delay element 1.
This corresponds to the delay time DL2 of 2. Therefore, as a result, the input pulse signal IN is obtained with its rising edge delayed by DL1 and its falling edge delayed by DLZ, and the pulse width is increased by DL2-DL1.

FIG. 5 (al, Tbl shows the basic configuration using the AND element and its main input/output signal waveforms. In this embodiment, the OR gate 13 is used as an AND element, and Except that it was replaced with 14,
The configuration is the same as in the previous case, and the main input/output signal waveforms are as shown in the figure. That is, it can be seen that the delay time TD+, z^ of the rising edge of the output OUT corresponds to DL2, and the delay time TDTR^ of the falling edge corresponds to DLI, and the i4 pulse width thereof becomes smaller by DL2-DLI. In any case, as in the previous case, when the input pulse signal IN rises,
The falling edge is independently controlled by delay elements 11 and 12.
Furthermore, it can be set with high precision, and as a result, the overall delay time of the input pulse signal IN and its pulse width can be adjusted with high precision. When a circuit is inserted between the test signal generator 3 and the driver 4 in FIG. 1 to correspond to pulse signals, the timing relationship of two or more Norse signals given to the IC under test is as expected. It is possible to set it to something. When setting the timing relationship as desired, the delay characteristics of the pulse signal compatible σ) driver, etc. must be taken into consideration, and the delay time of the delay element in each digital delay circuit is used as a reference for all edges with the largest delay time. Needless to say, it should be determined.

Next, modified configuration aspects of the digital delay circuit according to the present invention will be explained.

6(al) and (bl) respectively show a modified configuration of the one shown in FIG. 4(al). First, to explain from the structure shown in FIG. The input pulse signal IN and the input switch No. 8 IN via the delay elements 15 and 16' are connected to the OR gate 13.
It is designed to be logically summed. Therefore, the output O
The delay time of the rising edge of UT corresponds to the delay time DL3 of the delay element 15, and that of the falling edge corresponds to the delay time DL3 of the delay element 15.
It can be seen that the delay time of 6 corresponds to the phases of L3 and DL4. Also, what is shown in Figure 6 (bl) is
input/? Input via delay signal IN and delay element 16K
The output signal OUT is logically summed with the error signal IN, and the output OUT ft is taken out from the delay element 15.

It is clear that even with this configuration, the same result as shown in FIG. It goes without saying that a device using .

The basic aspects and modifications of the digital delay circuit according to the present invention have been described above, but from a practical standpoint, there may be cases where it is necessary to selectively switch and use either the OR function or the AND function.

FIG. 7 shows an example of the configuration of a digital delay circuit in which selective switching is considered, and FIG. 8(a) shows the configuration.

(b) shows an equivalent circuit when operating as an OR function or an AND function. Selection mode signal C0N
While T is in the so-called 'O' state, the exclusive OR darts 17, 2] function simply as passing darts, so the delay elements 18, 19 and the OR gate addition function as one OR gates. In addition, when it is in the so-called 11'' state, the exclusive OR function (17, 2) functions as an inverter, and as a result, it operates as an AND function. That's why. In addition, when replacing the OR gate 20 with an AND dart (well, if the selection mode signal C0NT is 10''
``In the state of moving platform (ma=filling function), ``1''
If it is in the state [&, it will operate as a disjunction function.

Furthermore, by using all the combinations of the basic delay circuits 1-) according to the present invention, it is possible to continuously make the /4' pulse width variable from shortening to widening without performing special switching control. . FIG. 9 shows the combination σ) -f+J, and the output of the delay circuit σ) by the OR gate has a logic interval (σ even if all the delay circuits are configured by gates).

Moreover, even if the OR gate and the AND gate are replaced here, the same effect can be obtained. There is a logical sum element consisting of one delay element 755 whose delay time is variable or fixed (℃・& logical product element σ) There is a delay time variable or fixed on the input side or output side℃・& In this case, other delay elements are further arranged.

Therefore, according to the present invention, it is possible to obtain the effect that the rising edge and falling edge of the input pulse signal can be independently and precisely controlled with delay flJ.

[Brief explanation of drawings]

Figure 1 shows the general configuration of the logic IC test equipment.
Figures 2 (al, bl) are diagrams for explaining the case where the set time, hold time, etc. are measured using a D-type flip 70 as an example of the logic IC to be tested. FIG. 3 is a diagram for explaining that even drivers with the same specifications have different output characteristics, and FIG. Diagrams showing the configuration mode and its main part input/output signal waveforms, Fig. 5 (al, (b)
) is a diagram showing the basic configuration mode using the AND element and its main part input/output signal waveforms, and FIG. 6 (at, (bl
FIG. 7 is a diagram showing a modified configuration of the digital delay circuit according to the present invention, and FIG. Figures 8(al and bl) are diagrams showing equivalent circuits when the logical sum function and logical y* function are selected, respectively, and Figure 9 shows an example of a combination of basic delay circuits according to the present invention. 11, 12...Delay element, 13...OR gate (
logical sum element), 14...and dart (logical product element)
. Representative Patent Attorney Tadashi Akimoto Business 1 Figure 2 (a) Figure 3 Figure 4 (a) Figure 4 (b) TDLEA TDTRA Figure 5 (a) Figure 5 (b) Figure 6 (a) ) Figure 7 JNI Figure 8 (a) Figure 18 (b) Figure 9 1

Claims (1)

[Claims] A logical sum element or a logical product element in which one delay element with a variable or fixed delay time is arranged on the input side, or another delay element with a variable or fixed delay time on the input side or output side. Furthermore, a digital delay circuit with all features of the arrangement is provided.