JPS60103643A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The invention relates to a gate array master slice integrated circuit device in which basic cells such as field effect transistors are arranged in an array and an arbitrary logic circuit is formed by a wiring pattern. In particular, the present invention relates to a semiconductor device in which a conductive path made of a gate electrode material is used as wiring to achieve higher integration.

(b) Background of technology Today, as large-scale integration becomes a big deal, there is a remarkable trend toward high-mix, low-volume production.
The production of large-scale integrated N-way using LICE30,000 is attracting attention.

The master slicing method is a method in which % basic element set I (usually a basic 1g1j6 consisting of multiple transistors and resistors) t-1 is prepared in advance on a large lid in one semiconductor chip (chip), and Then, a wiring mask is created and these transistors and resistors are connected to complete a large-scale integrated circuit having the desired electrical single-path operation.

According to the master slicing method, the basic element set consisting of transistors, resistors, etc. is formed in large quantities in advance, so when a request for independent development of a product arises, only the wiring mask needs to be made, which shortens the development period. be shortened. In addition, since the basic element set can be commonly used in various large-scale integrated circuits, development costs are also reduced. Such master slice large-scale integrated circuits are
Generally, a set of basic elements such as transistors and resistors are arranged in an orderly matrix in a desired area of a semiconductor chip, and by standardizing them in this way, automatic placement and wiring processing using a computer can be effectively adopted. be done.

The basic element set is generally called a basic cell, and gate array integrated WR devices are often used, in which basic cells are arranged in an array, and rounded input/output cells and input/output pads for forming peripheral circuits are arranged around the basic cells. has been
In addition, there is a strong desire to respond to the diversification of user requirements. Conventional Technology and Problems The basic cell is constructed using a complementary MO8 (MO8) field effect transistor (PET) as shown in Figure 1. IL)
, CMOS configured as shown in (b) and (e)
Gate arrays are most commonly used. FIG. 1(a) shows the most typical example of basic cells BC. This basic cell consists of two p-channel MOS F
E T + Tra, 5Tra2 and 2 n-channel A
/MOS FET r Tram *Tra. Transistors of the same channel share the source or drain region past or Na54, and
GaS-Qa, -Ga, or Ga, -Ga in which L and Tra3 and Tram and Tra4 are respectively directly connected
4- Gas 'fr.

- are separated from the gate.

The basic cell shown in Figure 1(c) is p-channel A.
/MOS FET # Trcl # TrCy +
Trcs and n-channel MO8FET e Tra4e
TrclI# Trcs, adjacent FETs of the same channel, for example, Trcs and T-rc, share a source or drain region Pcm, and Trcl
Gate Gc@-Ga4- to which Tra4 etc. are directly connected
FIG. 2(a) * (bt * (c) +
(0 shown in ψ Figure 2 (a), (b), (c)
, (d) are two-person NAND gate and two-person NAND gate, respectively.
OR gate, 4-person NAND gate, and 2-person AND
Two-man power NOR inputting the output of two and this two-man power AND
It constitutes a logic gate consisting of. Figure 2 (asun=
(bt) -(+!1)-(dl) is shown in Figure 2(a)
−(bJ, (cJ, (dJ) are each logic gate@Given.The unit of these logic gates will be called a unit cell UC.0And this unit cell is composed of at least one basic cell. ,
There are some things that exhibit logical functions, as shown in Figure 2 (a).
The O marks in (b), (c), and (d) are 5i-At contact holes C, which are necessarily used to connect the wiring between each wiring layer.

In Fig. 2 (IL)-(at), P channel MO8
F E T + Trs + Tr2 have a common drain D1, and each source if St # St has 5i
A node for power supply VCC is provided through the -At contact hole C. On the other hand, n-channel MOS
F E T Tra e Tr4 is the drain D of Trm
The source S4 of 3 and Tr is common, and ■ of Tr4 is Trl
+ Connect to DI of Trt, and connect 5t- to source S of Tg.
A power supply Vt+ pattern is provided through the At contact hole C. Then, the gate terminals A, B1 are inputs, and the output X1 is taken out from the drain D of Try, the drain D4 of Tr4, and the drain D4 of Tr4 through an 8l-At contact hole C. This logical formula is Xt = At
A two-man power NAND logic gate is configured in which the output is at the high level only when the input A1#BK is at the %H level, and the output is at the %H level under other conditions.

In Figure 2 (b) and (bs), p channel MO8F
ET Trg a Tra l n channel MO8
The FET Try*Tg is arranged in the same manner as in FIG. 2(a).

The source of the FET Tr is arranged in the pattern of the power supply Vcc via the 5t-At contact hole C, and the source of the Tr is the drain of the Try.
-r, is connected to the region forming the drain through a 5i-At contact. The source of the FET Tr and the source of the FET are connected to the pattern of the power supply vcIψ.
Gate A□B*u FE wired via At contact hole C〇and metal wired
The respective gates of TTrB and Try #FET Tr6 and Tr6 are connected to form a close terminal. Sara KF
Output X is taken out from the drain of ETTra via S1-A4 contact hole C. Also, as shown in the figure, an output voltage is taken out from a common region which is the drain of the FET Tr and the drain of Tg via a 5l-Atl contact hole C.

Therefore, as a result of the wiring of m FETs Tr@~Trl, a two-manpower NOR (Xz = At "Bt) logic gate will be constructed. Therefore, this means that when both inputs At and B are %Ll, %Hl level is output, and under other conditions, the Qi Ll level is output.

Figure 2 (c) = (at) is a p-channel FET
Tr12sn channel FET Trtx ~TrI
m and twice the 7tBC shown in FIG. 2(a), and as mentioned above, it is wired through the 8l-At contact hole C and is connected to a 4-person NAND (xs=Aa@B!@csIID8
) There is a list of configurations. The FET Tr4 and Trts a
FET Trto and Tr14 tFETTrtt and Tr
Metal wiring is provided to the gates of ts*FLTTTrt* and TrB, respectively, and the inputs As1Bs, c8 . The 0 output X3, which is arranged so as to be able to take out D and D, is wired so that it can be taken out from the PE.

When Bs-C5-DB are all at the HI level, the output X3 is at the LL level, and under other conditions, the output is at the 1 HL level.

Similarly to FIG. 2(c), FIGS. 2(d) and 2(dl) have a configuration in which P-channel FETs Trsy to Trio x and n-channel FETs Tru to TTr4 are arranged, and a logical formula can be taken out.

Although the above example shows an example in which four types of logic gates are wired, other unit cells can also be constructed by changing the mask bar 1-7 and performing the wiring process. In the wiring process, the wiring layers are stacked, and the distance between each wiring layer is 5t.
-Connection is made through the At contact hole C.

In a gate array LSI, as shown in FIG. 3, basic cells BC are usually arranged in an array in the center of the chip, and around the basic cells BC are provided an input/output circuit I10 necessary for connection with the outside of the LSI. An input/output cover and a door P are provided outside the output circuits I and 10. There is a wiring channel region mark in the middle of the basic cells BC arranged in an array, so that wiring can be done using At or the like.

CMOS gate array wiring is usually done using two wiring layers, and wiring within a unit cell is generally done in the first layer within that area, and wiring between unit cells, input/output, etc. The fourth wiring layer and the second wiring layer in the wiring channel region are applied to the wiring. In large-scale logic gate LSIs, most of the arrangement of unit cells and the wiring between unit cells and input/output circuits are automatically designed using a computer.

FIG. 4 shows a conventional example of the above-mentioned wiring outside the unit cell. As seen in the figure, a plurality of basic cell arrays are provided in a plurality of rows sandwiching a wiring channel region CH. The wiring shown by solid lines parallel to the Beta and Qcell arrays in the wiring channel region is the first layer At wiring layer LA,
The wiring shown by the broken line crossing over the cell array is the second layer At wiring layer LB. The 0 mark at the intersection of both wirings is a contact hole that connects the wiring in both layers, and the O mark shown on the basic cell BC frame is the connection between the 2nd layer wiring and the 1st layer wiring or gate electrode in the unit cell. FIG. 5 shows a schematic cross-sectional view taken across the 0 wiring channel region CH'ft showing the connection with the 0 wiring channel region CH'ft.

In the figure, 1 is a semiconductor substrate, 2 is a field oxide film,
3 is a gate electrode, 5 and 7 are interlayer insulating films, and 6 is a first Mi
Wirings LA and 8 are second layer wirings LB.

As explained above, when performing wiring, as the scale of the circuit increases, the number of wires also increases almost proportionally. h'), and the length of each wiring also increases. In addition, the increase in the number of wires causes design difficulties and the operating time of the computer increases rapidly, resulting in problems such as an increase in unconnected wires and a so-called delay in connection. In addition, it is possible to cope with the increase in the wiring area by using a new wiring layer, that is, a third layer of metal wiring, but as mentioned above, this also imposes a large burden on automatic design, and There is a problem in that the LSI mask slicing process becomes more complicated, resulting in a decrease in yield.

On the other hand, as an effective countermeasure against increasing the scale of logic circuits,
There is a way to reduce the number of wiring lines to be designed at the automatic design stage by defining the logic of the unit cell as 1.
This idea can be used not only for CMOS games but also for all logic VLS. However, as the logic within a unit cell increases, the number of wires within it also increases, so wiring within a unit cell cannot be realized only with the first layer of wiring on that area, and the wiring between unit cells and inputs increases. There is also a risk of using second layer wiring and wiring channel areas for output wiring, limiting automatic wiring design.

(d) Purpose of the Invention The present invention addresses the above-mentioned conventional problems and involves an increase in the number of patterning layers such as wiring layers, an increase in the number of process steps, and an enlargement of the wiring area, that is, an increase in the chip area. An object of the present invention is to provide a semiconductor device in which the scale of the gate array can be expanded without any problems.

(e) Structure of the Invention The object of the present invention is to provide a method in which basic cells made of field effect transistors are arranged in an array, and a conductive path made of a gate electrode material of the field effect transistors is arranged close to the basic cells. This is achieved by a semiconductor device in which wiring is constituted by the basic cell array, a wiring layer provided on the conductive path, and the conductive path.

(f) Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings.

FIG. 6 shows an example of a semiconductor substrate according to the invention, in which a line channel region is formed in an array shape using the same conductor layer as the gate electrode of a MOS FET of a basic cell and in the same process as the gate electrode. A maximum of about four conductive paths LG can be provided for one basic cell, but the conductive paths are electrically isolated from each other and between the conductive paths and the basic cell.

By providing a 2W1 wiring layer on the semiconductor substrate, a schematic cross-sectional view across the wiring channel region of the gate array LSI according to the invention becomes as shown in FIG. In the figure, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a gate electrode, 4 is the conductive path LG, 5 and 7 are interlayer insulation films, 6 is a first layer wiring LA, and 8 is a second layer wiring LB. The conductive path LG shown in FIG. 6 may be made long enough to reach inside the basic cell area as usual, and may be treated as an input/output terminal of wiring within the unit cell, or may be terminated outside the basic cell area. The connection may be treated as a unit cell external wiring. In either case, the first layer wiring LA is usually used to connect the unit cell and the conductive path LG. According to this structure, the connection wiring within the unit cell can be slightly extended if necessary, and the connection point of the gate electrode and the conductive path L
Although the first layer wiring LA is provided between the G and the end seats, this does not impose any restrictions on the wiring between unit cells. Note that connecting the gate electrode and the second layer wiring LB via the first layer wiring LA has often been done in the past.

As mentioned above, since the conductive path array LG can be arranged in high density, one conductive path LG is normally used for only one wiring.The present invention was applied to the connection example shown in FIG. 4 earlier. An example of wiring is shown in FIG. Similarly to FIG. 4, the first layer wiring LA is shown by a solid line, the second layer wiring LB is shown by a broken line, and the conductive path LG, which is a feature of the present invention, is shown by a dotted line. A connection unrelated to the conductive path LG, ◎ indicates a connection between the conductive path LG and the first layer wiring LA.

If you compare FIG. 8 with FIG. 4, it will be seen that the second layer wiring LB has been significantly reduced. By utilizing the channels indicated by these arrows, the total number of wiring lines can be increased without expanding the wiring area.

(9) According to the present invention, as in the example shown in FIG. 9, the arrangement order of the first layer wiring LA in the wiring channel region can be arbitrarily replaced using the conductive path βG.

Conventionally, the second layer wiring layer LB has been used for this purpose as well, and the structure of the present invention reduces the burden on the second layer wiring layer LB in this respect as well.

Further, according to the present invention, it is possible to connect basic cells separated by wiring channel regions without using the obvious wiring layer LB. This greatly expands the degree of freedom not only in wiring design but also in cell placement design.

(g) As described in detail, according to the present invention, for example, in an 0-S gate array integrated circuit device, the number of patterning layers and the process can be reduced by arranging conductive paths using gate electrode layers. New wiring layers can be created without increasing the number of processes.
By providing and configuring the structure on top of the upper wiring layer, the burden on the upper wiring layer, especially the second layer, can be greatly reduced, and the burden on the unit cell arrangement and wiring can be greatly reduced. The degree of freedom increases, and it becomes possible to expand the wiring scale or reduce the area of the wiring area without enlarging the wiring area. Furthermore, it is also possible to use this margin to increase the number of basic cells and increase the scale of integration.

Furthermore, the increase in the degree of freedom in unit cell arrangement and wiring facilitates the design, and has the effect of optimizing the circuit configuration and improving characteristics.

[Brief explanation of the drawing]

FIGS. 1(a), (b), and (e) are diagrams showing examples of CMOS basic cells, FIGS. 2(a) to (d) are diagrams showing examples of unit cells, and FIGS. 2(al) to (dl) is an equivalent circuit diagram of the unit cell, FIG. 3 is a plan view showing the arrangement of the cell array of the CMOS gate array LSI substrate, FIG. 4 is a plan view showing an example of a conventional wiring pattern, and FIG. 5 is a conventional 6 is an enlarged plan view of essential parts showing an embodiment of the present invention, FIG. 7 is a sectional view showing an example of a wiring channel region of an embodiment of the present invention, FIGS. FIG. 9 is a plan view showing an example of a wiring pattern according to the present invention. In the figure, BC is a basic cell, CHF1 wiring channel region, Ilo is an input/output cell region, P is an input/output pad, LG is a conductive path according to the present invention, LA is a first layer wiring, LB
2-layer wiring, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a gate electrode, 4 is a conductive path LG, 5 and 7 are interlayer insulation films, 6 is a first layer wiring LA, 8 is a second layer wiring Indicates LB. Agent Patent Attorney Hiroshi Matsuoka Shibu Inspection (口（α） （例（C）、Ω〜N 滲 3 口 Single 42 lobes S 口≦

Claims (2)

[Claims] (1) Basic cells made of field effect transistors are arranged in a play shape, and conductive paths made of a gate electrode material of the field effect transistors are arranged close to the basic cells, and the page, the cell array, and the 1. A semiconductor device characterized in that wiring is constituted by a wiring layer provided on a conductive path and the conductive path. (2) The semiconductor device according to claim 1, wherein a plurality of the four electric paths are not provided in a wiring channel region adjacent to the basic cell array.