JPS60104934U - data transmission equipment - Google Patents
data transmission equipmentInfo
- Publication number
- JPS60104934U JPS60104934U JP19552283U JP19552283U JPS60104934U JP S60104934 U JPS60104934 U JP S60104934U JP 19552283 U JP19552283 U JP 19552283U JP 19552283 U JP19552283 U JP 19552283U JP S60104934 U JPS60104934 U JP S60104934U
- Authority
- JP
- Japan
- Prior art keywords
- bit
- pulse
- data transmission
- data
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Input From Keyboards Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来のキーボード分離形パソコンのキーボー
ド周辺回路を示すブロック図、第２図は、本考案による
キーボード分離形パソコンのキーボード周辺回路の一実
施例を示すブ爾ツク図、第３図は、第２図の動作を説明
するための各部の信号のタイミングチャートである。
１・・・キーボードとパソコン本体を結ぶ接続線、２．
３・・・カウンタ、４・・・デー′タデコーダ、５・・
・キーボードマトリクス、６・・・データセレクタ、７
・・・Ｄラッチ、８・・・スリーステートバッファ、９
・・・スイッチ、１０・・・Ｄラッチ、１１・・・イン
バータ。FIG. 1 is a block diagram showing a keyboard peripheral circuit of a conventional keyboard-separated type personal computer, FIG. 2 is a block diagram showing an embodiment of the keyboard peripheral circuit of a keyboard-separated type personal computer according to the present invention, and FIG. 2 is a timing chart of signals of each part for explaining the operation of FIG. 2. FIG. 1... Connection line connecting the keyboard and the computer body, 2.
3... Counter, 4... Data decoder, 5...
・Keyboard matrix, 6...Data selector, 7
...D latch, 8... Three-state buffer, 9
...Switch, 10...D latch, 11...Inverter.
Claims (1)
の送受信を行なう装置１、装置２に具備し、送信側の装
置１にｎビット（ｍ＞ｎ）データとｍビットカラン“り
出力のｎビットが一致したときのみパルスを出力する回
路を具備し、受信側の装置２に該パルスによりｍビット
カウンタ出力のｎビットをラッチしてｎビットデータを
デコードする回路を具備した装置において、カウンタの
走査−巡毎に送受信側番々のカウンタを同時にリセット
することを特徴とするデータ伝送装置。Devices 1 and 2 that transmit and receive data are equipped with m-bit counters that operate on the same clock signal, and the n-bit (m>n) data in device 1 on the sending side matches the n-bit output of the m-bit counter. In a device that is equipped with a circuit that outputs a pulse only when a pulse is output, and a circuit that latches n bits of an m-bit counter output using the pulse and decodes n-bit data in the device 2 on the receiving side, the scanning-circulation of the counter is A data transmission device characterized in that counters on a transmitting and receiving side are reset at the same time each time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19552283U JPS60104934U (en) | 1983-12-21 | 1983-12-21 | data transmission equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19552283U JPS60104934U (en) | 1983-12-21 | 1983-12-21 | data transmission equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60104934U true JPS60104934U (en) | 1985-07-17 |
Family
ID=30753118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19552283U Pending JPS60104934U (en) | 1983-12-21 | 1983-12-21 | data transmission equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60104934U (en) |
-
1983
- 1983-12-21 JP JP19552283U patent/JPS60104934U/en active Pending
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