JPS599639U - code conversion circuit - Google Patents
code conversion circuitInfo
- Publication number
- JPS599639U JPS599639U JP10438882U JP10438882U JPS599639U JP S599639 U JPS599639 U JP S599639U JP 10438882 U JP10438882 U JP 10438882U JP 10438882 U JP10438882 U JP 10438882U JP S599639 U JPS599639 U JP S599639U
- Authority
- JP
- Japan
- Prior art keywords
- conversion circuit
- code conversion
- exclusive
- output terminal
- nth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は2進コードを示す図、第2図は本考案によるフ
ニド変換回路、第3図は本考案の動作説明図である。
1〜4・・・・・・信号入力端子、5〜7・・・・・・
排他論理和ゲート回路、8〜11・・・・・・信号出力
端子。FIG. 1 is a diagram showing a binary code, FIG. 2 is a Hunido conversion circuit according to the present invention, and FIG. 3 is an explanatory diagram of the operation of the present invention. 1-4...Signal input terminal, 5-7...
Exclusive OR gate circuit, 8 to 11...Signal output terminal.
Claims (1)
れる入力端子と、Nビットの符号間距離が1のグレイコ
ードを出力する出力端子と、N−1個の排他的論理和回
路を有し、i番目(i=1〜N−1)の排他的論理和回
路は入力信号の最下位ビットからi番目とi+1番目の
信号を入力し、各排他的論理和回路の出力を1〜N−1
番目の出力端子に接続しN番目の入力端子とN番目の出
力端子を直接接続することを特徴とするコード変換回路
。An input terminal that receives parallel binary signals of N bits (N is an integer of 2 or more), an output terminal that outputs a Gray code with an N-bit intersymbol distance of 1, and an exclusive OR of N-1 pieces. The i-th (i=1 to N-1) exclusive OR circuit inputs the i-th and i+1-th signals from the least significant bit of the input signal, and the output of each exclusive OR circuit is 1~N-1
A code conversion circuit characterized in that the code conversion circuit is connected to the Nth output terminal, and directly connects the Nth input terminal and the Nth output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10438882U JPS599639U (en) | 1982-07-12 | 1982-07-12 | code conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10438882U JPS599639U (en) | 1982-07-12 | 1982-07-12 | code conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS599639U true JPS599639U (en) | 1984-01-21 |
Family
ID=30245136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10438882U Pending JPS599639U (en) | 1982-07-12 | 1982-07-12 | code conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS599639U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01135929U (en) * | 1988-03-14 | 1989-09-18 | ||
| JPH0232831U (en) * | 1988-08-26 | 1990-03-01 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50155147A (en) * | 1974-06-03 | 1975-12-15 |
-
1982
- 1982-07-12 JP JP10438882U patent/JPS599639U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50155147A (en) * | 1974-06-03 | 1975-12-15 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01135929U (en) * | 1988-03-14 | 1989-09-18 | ||
| JPH0232831U (en) * | 1988-08-26 | 1990-03-01 |
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