JPS60120680A - data processing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data processing system, and more particularly, the present invention relates to a data processing system, and in particular, after transmitting a plurality of data blocks each including synchronization data, address data for committing to a memory, and information data, at least a part of the data blocks is transmitted. This invention relates to a data processing system for loading data into memory. <Description of the prior art> Generally, in the data processing system of this tumor.

After transmission 1 For example, after recording and reproduction are performed, it is necessary to perform processing such as correcting code errors and arranging information data, so the transmitted data is temporarily stored in memory such as RAM (random access memory). There must be. At that time, all data calculation positions should be added in front of it.
According to the address data in L, one of the memory must be placed in a fixed location.

In fact, address data is also transmitted in the same way as blueprint data, so there are no dropouts, problems, or problems.
There is a possibility of EiJ causing code errors due to code amount interference or the like. Therefore, depending on the address data that has been transmitted, it is not possible to write information data into the memory in accordance with the address data that has been transmitted.

Therefore, data similar to the address data is created by counting the synchronization data in each data block at the same time as this address data.

There is also a method of completely controlling the annotation position in memory using a so-called internal address counter. Since the counter also counts the transmitted synchronization data, there is a risk that the count value may be distorted by loss of synchronization data or by sound, etc. to) Particularly in this case, there is a danger that once a count error is made, all data transmitted thereafter will become invalid.

<Objective of the Invention> In view of the above-mentioned drawbacks, the present invention has an object to provide a data processing system that can control the 1) loading position into a memory very accurately.

<J: Description of Embodiments> Hereinafter, a data processing system of the present invention will be described in detail using an embodiment in which the data processing system of the present invention is applied to a recording/reproducing system of Digital Audio No. 49 in a video tape recorder (VTR).

FIG. 1 is a schematic diagram showing a tape running system of a VTR according to an embodiment of the present invention. In Figure 1, 1 is a rotating drum.

2.3 is a rotary head, 4 is a magnetic tape, 5.6.
Reference numerals 7 and 8 designate movable guide posts for pulling out the tape 4 from the cassette 10 and winding it around the drum 1, and 11 and 12 designate guide posts. 180° on drum 1 as shown.
Heads 2 and 3 arranged with a phase of 9 are respectively 9.
While moving from point A to point B in the figure, a digital audio signal is transferred from point B to point C, and a video signal is transferred from tape 4 to point C.
Record while forming a helical track on the top.

FIG. 2 is a diagram showing the recording format on the tape 4 by the VTR of FIG. Reference numeral 13 shown in FIG. 2 is an area where video signals for 1 field are recorded, and 14 is an area where digital audio signals outside the 1 field period are recorded. The digital audio signal recorded in the area 14 is, for example, a sampled audio signal 'f
: Converted to PCM.

It is assumed that the time axis is further compressed and FM modulation is recorded.

Next, an example of the data format of this digital audio signal will be explained using FIG. 3. The formant shown in FIG. 3 is an audio signal outside the l field period, and the sampling frequency is 480 fv, where fv is the field frequency. .

In FIG. 3, bo to b1.19 indicate f-ta blocks, respectively. Also AU~A l l! J &, I: Addressing data words, QO to Q, 1.19 and E, respectively.
)0~P119t, ↓ parity word for correcting each error,
r,, o~L 479 is the L channel audio signal.
Day word of issue.

R(1"-R479 is the data word of the first digit number. Each data block has t
The same data for 1 in the 1 part, the 1 word for addressing, 8 words of audio code data, 2 words of error correction data, and the CRCC (Cyclic
ic Redundancy Chcclc Cotl
e) is inclusive 1 no'1. For example, tlid::ubiyto, t2 to tizi are composed of 8 bits, and t+3+ is composed of 16 bits. - The well-known cross-interleaving method is used to form the quality words, and of course the ml' node interleaving shown in Figure 1 is also used. ing.

The data matrix written from the above-mentioned 9+J@format VC is shown in FIG. 4 in units of data blocks each having address data and synchronization data.
<Transmitted sequentially. Then, one data matrix is recorded in the area 14 as it is completed.

A (1,
QO, LO, L60. Li2O, Li2O, )'0.
L240°L3 (10, L360. L420. b
Data for synchronization of CB, CC, bl of O; A1. Ql,
RO, R60... Li1O's (,
Recorded at RCC trench.

Next, when reproducing this data, errors in each data block are detected by CRCC.

It is necessary to search through the entire matrix using the parity word. Therefore, once again, write these to RAM.
It must be stored in the temple's memory before processing. At this time, all 10 words of data are loaded into the AM according to the address data added immediately before.

FIG. 5 is a diagram showing the state on the RAM of d-1'n. The 10 words of data of each data block described above are recorded in areas on the RAM corresponding to each address AO to A119. Further, in the portion shown by Ii'rag in FIG. 5, which is subjected to IS for each block, the error search result data corresponding to each word of the 10-word data is stored. This data (flag data) (=-1+, -
Correct or wrong each word of the 10 words 'olt or l J,
It is assumed that 7 is included in l. The Frag part from 1JIJ only needs to have at least 10 bits (for example, 2 bytes=1 (i bit)).

In this way, the data corresponding to the audio signal for one field period is stored on the ltAM, but before this, a data error has been detected for each data block by the CRCC. At this time, if an error is detected in one data block by cf7cc, it means that an error has occurred somewhere in the 10 word data or the address data. Therefore, in this case, when writing address data to RAMK, as mentioned above, there is a risk greater than V.If the rear address data is incorrect, the data in that block will be invalid. This has a negative effect not only on error detection for all data, but also on error detection for all data.

FIG. 6 is a block diagram showing a reproduction data processing system of a VTR as an embodiment of the present invention. In Figure 6, 21 is
This is a terminal to which the data reproduced by the heads 2 and 3 and FM demodulated is input. The data input format at this time is as shown in the fourth example. This input data is CRC
C NAEC circuit 22° synchronization signal detection circuit 23. The 411 circuit 22 supplies the CRCC as described above to the data separator 25. The 2 circuit 23 separates the synchronization data, and the separator 25 separates the address data 1 and 10 word data.

The synchronization data detected by the synchronization signal detection circuit 23 is
1) The data separator 25 operates in the 1st mode. On the other hand, this detected synchronization data is sent to the internal counter 24 (Jla
Re,! By counting this synchronization data with the counter 24, it is possible to know the address at which the currently input data block should be written.

The cutting edge of the data separator 25 is supplied to the address extraction circuit 26)1. ,, in the circuit 26 i'C, 1 tres de one taka 14 (k J tL Zl. Thus i(l et al. 1st
The address data and the address value output from the counter 24 described in 1111 are supplied to the comparison circuit 27.
jl, etc. are the same, but 9 is grouped 1st. Ru.

This discrimination output is fed to the control circuit 28)1. Ru. 1, the control circuit 28 has a CIECCFL circuit 22.
The detection output of one prefecture for each data block obtained from
I'; 38. iii. The control circuit 28 controls the data selector 29 and the load control circuit 31 based on these two information sounds.

Based on the output of the data selector 29) and the control circuit 2B,
A, 10 word data to M2O j) Included address 21: , In response to the address data extracted by the address 1/s extraction circuit 26, it is determined whether the output is determined by the output of the U section counter 24. Choose the decisive sword. Now.

CRCC's "check blade is l'" is the output corresponding to 1E-J, and L is the output corresponding to 1E-J.Since no error has occurred in the address data extracted by the address extraction circuit 26, it is output via the A terminal of the selector 29. Using the address data obtained, t(A
Data is loaded into M30. However, if this address data and the output of the internal counter 24 match, either one may be used.

By the way, now the CRCC check output corresponds to "correct" 1
-, and the address data extracted by the address extraction circuit 26 and the internal counter 2 are output by the comparison circuit 27.
It is determined that the output of 4 does not match) 1. Let's think about a time when At this time, there is no code error in the transmitted address data, so 81 (counter 2)
4 counts synchronization data and counts one stroke, or noise. However, the internal counter 24
Once the count value becomes incorrect, all subsequent count values will become incorrect, which is extremely dangerous.

Therefore, in this case, the shared address extraction circuit 26 extracts 7.
The transmitted address data is supplied to the internal counter 24 via the A terminal of the selector 29 and the C terminal of the load control circuit 31, and the output of the internal counter 24 is made to match the transmitted address data. In this way -rtoC
'The address value (
again has a value depending on 'kf'.

In short, if the naenoku output of CI7CC corresponds to "city i", it is extracted by the address extraction circuit 26 t'1.
- There is a danger in using /:) address data.

The output of the internal counter 24 is used.

Particularly at this time, when the comparison circuit 27 determines that the address data extracted from each of the γ-trace payoff circuits 11 and the output of the internal counter 24 do not match.

4) Since the whiteness is extremely high, the output of the whitening counter 24 is set to the selector 29.
R, AM3 (Boo\□IJI', K
F f, te 1. Control the F-inclusive address 1. However, in this case as well, when the extracted address data and the output of the internal counter 24 match, VC may use either one.In this case, the extracted address data and the inner t1
It is natural to assume that both outputs of the 4X counter 24 are error-free.

Even when there is a possibility of a code error in the address data, the output of the internal address counters 2 and 1 is always a reliable value as described above.

A late address to 1°C AM30 will always be reliable.

FIG. 7 is a diagram showing an example of the configuration of the f ftllJ circuit 28 shown in FIG. 6. In Figure 7, 41 is CRCC
A terminal to which the output from the check circuit 22 is supplied.

When there is a code error in the data block being transmitted, a high level signal J' is input. Reference numeral 42 denotes a terminal to which the output of the comparison circuit 27 is supplied, and a high level signal is inputted when the output of the internal counter 24 and the address data obtained from the address sampling circuit 26 do not match. 43 is the data selector 29? I? lI This is an output terminal for the signal supplied to the mu terminal, and when the output signal is low level, it selects the address data obtained from the address extracting circuit 26 via the data selector 29 A terminal, and selects the address data obtained from the internal counter 24 at a high level. Select all outputs. 44 is a load control circuit 31
This is the output terminal for the signal supplied to the 0 control Mil Qm child, and the load control circuit 31 is activated only when the output signal is at a high level.
The f address data i, from the selector 29 is supplied to the internal counter via the C terminal.

45t inverter, 46 is an AND gate. Therefore, the data selector 29 depends on the output of the CRCC naenoku 1st generation 22 and selects the jut operation 17. When there is error number 41 in the data block, the output of internal counter 24 is 1.
1, p IICit selects the low transmitted γ/SD. On the other hand, load tii control circuit: 3]ke CILCC
Only when the output of the check circuit is at a low level and the output of the comparison circuit 27 is at a high level, address data from the controller 29 is supplied to the internal counter 24 (a; not included). -=Knob/Sf-G Chronok has no errors, and relative rotation +
1iis 27 f′ is 11111/l (1) When the ratio 11 is negative 1, the inner ↑′ small counter 2
Address data 11. (N match ＼
Ze2. ) like<fill<. .

In this way, the selection output by the selector 20 is also determined according to the address value.By determining the loading address of the AM30-\, it is possible to transfer data to the RAM M2O using only the transmitted address data in the conventional system. Determining the embedded address by kneading using only the output of the /J counter and using only the output of the counter, all of the shortcomings that occur when using the contamination can be compensated for by each other, and the transfer to memory such as RAM of,
-1) The inclusion point j' can be determined very accurately.

~Also, as soon as the internal counter 24 exceeds the count ε, the IJf function is activated to correct it.

In this way, the power stored in the RAIVff30, the 10-word data IrJ', and the black data by the non-standard word as described above are added, and the error correction is performed. It was output as No. 18. .

In addition, in the 1st and 11th implementation of +1d, there was a failure of RAM.

Response fi11 control is 16 in @ IS counter output 1
“Do it at 6pm.

There is no coding error in one data block being transmitted by the CIt CC check circuit 22, and the sword/tsu comparison circuit
[The output data of the internal counter is made to match the transmitted address data only when the above comparison does not match, and the RA
A similar effect can be obtained by configuring the address data transmitted to be used for the built-in address control of M.

Furthermore, in the above embodiment, V′11′f is also V′11′−C1
) CM Recording I 1J Ushisano 1-ru Audio E → Uzen f
I'm taking it to Rir.

/1 when transmitting multiple data blocks including synchronization data, 7' address data, and 1'11 information data.
＼There is no possibility that the effect of 11.lIk will be avoided by C applying the invention.

Explanation of effects> f4. 9. According to this data processing system. In response to the instruction, the address data (t←) in the data block (according to the instruction of C-den-no-in-juku) is to change the address counter's skewer (by the IC, the address counter's Output sound ′Iδ
Assume that It', r :+:ri can be stored in the memory as a result, σ), 51 included, nohbut l/ 7.4... It is possible to determine C very accurately n (J(i two - This is the data p, 1jlj due to ε of the included address.
In addition to the effect (, the power defense 1j 2), it is always cheap data transmission and the tape ``l('↓
111-4 to 9 became rIJ capable.

[Brief explanation of the drawing]

r1! FIG. 1 is a schematic diagram showing a tape running system of V Tit which is an embodiment of the present invention. Figure 2 shows the recording format on the tape by the VTR in Figure 1.
) - 1° 1°Frr, 4 [%l I'j showing the timing chart showing the transmission order of data. No. 51 No. 1&:ii also wrote the data (2) to AMJ2.
), 1 dap indicates jl shiba<1. Second, I will refer to this book's explanation σ1 as another example C) VTR
This is a block diagram that improves the reproduction data processing system J:lij system. FIG. 7 is a diagram showing an example of the -j-<ti control circuit shown in FIG. 6]. 22 is a CRCC check i times 1 circuit as an error detection means, 2:lJ same jυ1 data minute pi's circuit, 24 is a same sound b address counter, 25 is a data senor (rater), 26 is an atrenu sampling circuit, 27 is an atrenu sampling circuit. A comparison circuit as comparison means, 28 a control circuit, 29 data selectors, 30 a RAM as a memory, 3t a load hook circuit, AO to A119 address data, respectively. 5 sync is synchronization data, b O to b l l return;
Each L indicates a data block. 11, Ija person Canon Co., Ltd. Figure 1 Guan 1 Shou 7

Claims (1)

[Claims] 1) A data processing system for loading into a memory at least the information data in each block of a plurality of transmitted data blocks each including synchronization data, address data for loading into the memory, and information data, , an address counter that operates according to synchronization data in the transmitted data block; means for detecting code errors for each block; and address data in the transmitted data block. and means for comparing the output data of the address counter described in 1iif with the output data of the address counter described in 1iif, and the output data of the address counter described in C6jl according to the detection means and the comparison means described in riiJ. data processing/system that includes a means to match response data;