JPS60141075A - Detection circuit of line synchronizing code of g3 facsimile signal - Google Patents

Abstract

PURPOSE:To allow detection of EOL codes at a high speed with simple constitution and to offer flexibility with respect to code length of special codes by making it possible to detect EOL codes with a special format in a code strng by processing at every word without bit handling. CONSTITUTION:A sum of the number outputted by a register 4 and that of zero its which continue from the highest order of eight-bit data of an input to the lower order are outputted at an A side of a logical operation circuit 2. The number of zero bits which continue from the lower order to the higher order is outputted at a B side. A comparator 5 inputs the value of the logical operation circuit 2 at the A side, decides whether it is beyond 11, and when it is beyond 11, the comparator 5 outputs a detection signal of an EOL code. When fourth bit of the output signal at the B side is zero, a selector 3 is controlled, and the output value at the B side is inputted to an input of the registor 4. Then addition of new continuous zero bits is started. When fourth bit of the output signal at the B side is one, the output at the A side is set to an input of the registor 4 by a selector 3.

Description

[Detailed Description of the Invention] A. 7+Y- Industrial Application Field The present invention complies with Cci'i"i' Recommendation, T.4 (
(Q) Minkuri millimeter F14 pheasant tatami (mochi 7), ito・, 2,
2 in Human code, modified lead negative sign)
In the in-synchronization code (EOL code), which are standardized encoding methods such as modified Huffman coding, modified lead coding (MH coding method, M-coding power method), the main To detect the line synchronization code (EOL code, '000000000001' is assigned as the code) used to separate each scanning line, bit-shift the serial data using a shift register, etc., and set a fixed pattern bit by bit. It is detected by comparing it with

In addition, when these processes are implemented using a microprocessor, etc., it is necessary to
The received code is converted into parallel data regardless of the line synchronization code, and the parallel data is shifted one bit at a time and detected in the same manner as described above.

According to the conventional method, if the parallel data is n bits, it is necessary to perform one focus shift process n times, and if one shift is performed using the timing clock (1), the processing time will be extremely long. Also, test t1. Due to the code length of a special code, it is often necessary to increase the number of stages of shift registers, comparators, etc.9, and there is a lack of flexibility to change the code length of a special code.

C1 Object of the invention The object of the invention is to
It is an object of the present invention to provide a circuit that can detect a special line synchronization signal consisting of I at high speed with a simple configuration and has flexibility for the length of the special line synchronization signal.

2. Structure of the Invention The present invention provides an n-bit parallel register, and inputs the value of a 101-bit number that is continuous between the parallel output thereof and the previous data output from the next stage circuit, and stores the continuous data up to the current data. On the logic circuit that outputs the number of IO bits currently being detected and the number of consecutive 101 bits newly detected in the current data, the number of consecutive 1-() hits is the line synchronization signal. and a comparison circuit that determines whether the following conditions are satisfied.

E, Example The present invention will be described with reference to examples.

FIG. 1 is a circuit block diagram for detecting an EOL code in a G3 facsimile code using 8-bit parallel data. In the figure, 1 and 4 are each 8 bits,
It is a 4-bit register with an initial value of zero, and data is latched using the same clock. 2 is a logic circuit made up of memory, PLA, etc. that inputs the outputs of registers 1 and 4. Outputs the sum of the number of consecutive @0" bits (8 or more) and the number output from register 4. A pigeonhole where the sum is 16 or more outputs 15. Logic The B a+1+ output of circuit 2 has
Outputs the number of consecutive 0 bits from the lowest to the highest in the input 8-bit data. If there is at least one “1” in the 8-bit input data, E
Check whether the OL code is the final bit/ζ
Comparator 5 uses the 4th bit “0” of the B side output.
Make it effective.

At this time, the comparator 5 outputs the A side output of the logic circuit 2.
^ is input and compared to see if it is 2.11 or more, and if it is 11 or more, an EOL code detection signal is output.

The 4th bit of the B decompression output signal is lO", that is,
If there is at least one 111 in the data and there is a 1, control selector 3 and input the B side output candy to the input of register 4 to start adding a new number of consecutive "01 bits." The 4th bit of the Bπljl output signal is 51#, that is, the input 8-bit data is all 10".
In this case, the input side output is input to the register 4 by the selector 3.

According to the present invention, a special format of EC)Llq in a code string
-Q detection can be performed by word-by-word processing without bit handling, and since a shift register is not used, a shift clock is not required and the processing speed is increased. It has the advantage of greater flexibility than the conventional technology, as well as the flexibility of the code length.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention. 1 ・8 beat registers, 2 ・Logic 1! :! l path, 3... selector, 4... 4 bit register,
5 comparators. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A G3 facsimile code including a line synchronization code (BOL code) is received as an n-bit parallel signal, and the current reception (%nn
The number of consecutive 101's up to the received n-bit parallel signal before the bit parallel signal side and the number of consecutive 10's at the current received n-bit parallel signal (Jlt appearing at the beginning of the M number) are detected, and the EOL code is detected. 03] A line synchronization code detection circuit of Dokushimiri Hakugo.