JPH0242275B2 - - Google Patents

Description

Circuit 23 to stop A decoding circuit comprising:

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION The present invention relates to a decoding circuit for receiving variable length encoded image signals at a constant speed and decoding the variable length encoded signals.

Prior Art and Problems Various methods have been proposed for high-performance encoding in systems for encoding and transmitting image signals.
For example, a variable length encoding method is known that performs high-performance encoding by assigning the shortest code to the code with the highest probability of occurrence. In this variable length encoding method, image signals having different bit lengths of one sample value are transmitted at a constant speed. On the receiving side, this constant speed data is received and sequentially converted into fixed length codes by identifying the variable length code pattern.

FIG. 1 is a block diagram of the main parts of a conventional decoding circuit, in which 1 is an input terminal, 2 is a buffer memory, 3 is a flip-flop circuit, 4 is a multiplexer, 5 is a code conversion circuit, 6 is a control circuit, 7a, 7b, 9 is a flip-flop circuit, 8 is a special code detection circuit,
10 is an adder circuit, 11 is a selector, 12 is a comparison circuit, 13 is an OR circuit, 14 is an AND circuit, 16 is a decoding output terminal, CLK is a clock signal, and RCK is a read clock signal. Data received at a constant speed is sequentially written into the buffer memory 2, read out in parallel by a predetermined number of bits, for example, 8 bits at a time, and applied to the flip-flop circuit 3, multiplexer 4, and special code detection circuit 8.

The special code detection circuit 8 detects a special code of a variable length code string from the data read out from the buffer memory 2, and this special code is
For example, it is formed at the timing of a horizontal synchronization signal of an image signal on the transmitting side, and then a variable length code string is transmitted. That is, a variable length code string is transmitted between special codes. Note that control information may be inserted and transmitted after the special code. The leading bit position information of the special code obtained by detecting this special code is set in the flip-flop circuit 9.

Also, the flip-flop circuit 3 has a buffer memory 2.
For example, 8-bit data sequentially read out by the read clock signal RCK is set and inputted to the multiplexer 4 together with 8-bit data at the next read timing. Therefore, 16 bits are input to the multiplexer 4, and 8 bits are input to the code conversion circuit 5 in a format in which the code to be decoded at the bit position according to the read-out bit position information from the flip-flop circuit 7a is the first bit. The code conversion circuit 5 identifies a predetermined variable length code pattern according to the mode information etc. from the control circuit 6, inputs information indicating the length of the variable length code to the addition circuit 10, and The signal is converted into a code and output as a decoded output from the output terminal 16.

The adder circuit 10 receives the length information of the variable length code from the code converter circuit 5 and the flip-flop circuit 7a.
By adding the previous read bit position information from , information indicating the next read bit position is output.
The output of this adder circuit 10 and the special code detection circuit 8
The comparator circuit 12 compares the first bit position information of the special code detected by the special code and set in the flip-flop circuit 9, and controls the selector 11 unless there is a match or the first bit position information of the special code is smaller. The read bit position information of the output of the adder circuit 10 is set in the flip-flop circuit 7a, and in other cases, the selector 11 is controlled to set the leading bit position information of the special code set in the flip-flop circuit 9 to the flip-flop circuit 7a. Set it to Further, the output of the comparison circuit 12 when the selector 11 selects the first bit position information of the special code is set in the flip-flop circuit 7b, and the set output is applied to the control circuit 6 to notify that the special code has been detected. and control circuit 6
For example, if the special code is formed at the timing of horizontal synchronization, the decoding control of the image signal of the next scanning line is performed.

Based on the read bit position information of the output of the flip-flop circuit 7a, the multiplexer 4 selects the data to be added to the code conversion circuit 5, and also selects the data to be added to the adder circuit 1.
0 adds the bit position information and the code length information of the variable length code from the code conversion circuit 5, and for example, the read bit position information indicates the 5th bit and the code length information of the variable length code is 5 bits long. In this case, the next read bit position information output from the adder circuit 10 is the second bit of the 16 bits of data (in this example, 8 bits are processed in parallel) to be read at the next read clock. , 5 bits + 5 bits - 8 bits = 2 bits).

Reading of the buffer memory 2 is performed by the read clock signal RCK, and the AND circuit 14
The read clock signal RCK is outputted from.
Further, the clock signal CLK is applied as a clock signal to the flip-flop circuits 7a and 7b, and also to the AND circuit 14. Therefore, read clock signal RCK is output in accordance with the outputs of flip-flop circuits 7a and 7b.

In the conventional decoding circuit as described above, there is a delay time until the special code is detected, the selector 11 is controlled by the output of the comparison circuit 12, and the first bit position information set in the flip-flop circuit 9 is selected. This determines the operating speed of the decoding circuit, for example short key TTL
When configured with a bipolar ROM and a bipolar ROM, the operation time was limited to about 8 MHz due to the aforementioned delay time.

OBJECTS OF THE INVENTION It is an object of the present invention to enable high-speed operation with a relatively simple configuration.

Structure of the Invention The present invention includes a buffer memory 2 that receives code string data at a constant speed in which a control signal and a plurality of variable length codes are inserted between special codes of a predetermined bit pattern, A multiplexer 4 that reads and outputs data of a predetermined bit length from a bit position according to the read bit position information, inputs the data from the multiplexer, identifies a variable length code according to the variable length code rule, and converts the data into the variable length code. a code conversion circuit 5 that outputs code length information of the code converter, an adder circuit 10 that adds the code length information from the code conversion circuit and the read bit position information to obtain the next read bit position information, and detects the special code. a special code detection circuit 8 that outputs leading bit position information from the special code detection circuit; and a comparison circuit 1 that compares the leading bit position information from the special code detection circuit with the read bit position information used by the multiplexer.
2. When the comparison circuit finds a match or the first bit position information is smaller, the first bit position information is set as the next read bit position information;
In other cases, the selector 11 uses the output of the adder circuit as the next read bit position information, and when the special code is detected and the output of the comparator circuit controls the selector to select the read bit position information. , is characterized by comprising a circuit 23 for stopping reading from the buffer memory.

Examples will be described in detail below.

Embodiment of the Invention FIG. 2 shows the basic configuration of an embodiment of the present invention, in which the same symbols as in FIG. 1 indicate the same parts, 20 is an AND circuit, and 23 is a buffer memory read stop circuit. be. The differences from Figure 1 are as follows:
The comparison circuit 12 compares the first bit position information obtained by detecting the special code with the read bit position information set in the flip-flop circuit 7a, and indicates that there is a match or the first bit position information is smaller, and the special code is detected. As a result, the selector 11 is controlled by the output of the AND circuit 20,
The first bit position information is stored in the flip-flop circuit 7a.
is set to In the present invention, when the circuit part that sets the leading bit position and the special code are detected and the selector 11 is controlled by the output of the comparison circuit 12 to select the read bit position information, the reading from the buffer memory 2 is performed. Circuit to stop 2
It has 3. That is, when a special code is detected, the selector 11 can select the first bit position information based on the comparison result between the first bit position information and the current read bit position information. When is equal to or smaller than the next read bit position information, the next read clock signal RCK is output, and the next 8 bits are read from the buffer memory 2.
Decoding of the next variable length code can begin.
Therefore, it is possible to speed up the decoding process. Further, the buffer memory read stop circuit 23 allows the next special code to be detected without erroneously identifying the variable length code before the special code even if there is a data error.

In other words, the buffer memory read stop circuit 23 is
Even if a part of the special code is decoded as part of the variable length code data due to a transmission path error, etc.
This allows the data following the special code to be decoded normally.

FIG. 3 is a block diagram of essential parts of an embodiment of the present invention. In FIG. 3, the same symbols as in FIGS. 1 and 2 indicate the same parts, 18 to 20 are AND circuits, 21
2 is an inverter, 22 is an OR circuit, and 24 is a flip-flop circuit. The buffer memory read stop circuit 23 shown in FIG. 2 is composed of an AND circuit 18, an OR circuit 22, and the like. The first bit position information set in the flip-flop circuit 9 is n.
The code length information of the variable length code from the code conversion circuit 5 has an n-1 bit structure, and the code length information from the flip-flop circuit 7a to the multiplexer 4 and the adder circuit 1
The next read bit position information added to 0 is n-
In the case of a 1-bit configuration, the addition output of the adder circuit 10 has an n-bit configuration, and the selector 11 selects n bits of the output of the flip-flop circuit 9 or the adder circuit 10 and sets it in the flip-flop circuit 7a. The most significant bit of the first bit position information
The MSB is inverted by an inverter 21 and applied to a flip-flop circuit 24 and an OR circuit 22. Also, the most significant bit MSB is AND circuit 1
Added to 9,20.

The most significant bit MSB of the bit position information selected by the selector 11 is applied to the AND circuit 18 together with the output of the OR circuit 22. Comparison circuit 12
In this case, n bits of the most significant bit MSB and the n-1 bit set in the flip-flop circuit 7a are used as the next read bit position information, and n-1 of the first bit position information set in the flip-flop circuit 9 is used. The bits and the n bits with the output of the AND circuit 19 as the most significant bit MSB are added as leading bit position information and compared.
The comparison output is applied to AND circuit 20. When the special code is detected by the special code detection circuit 8, the most significant bit MSB of the first bit position information set in the flip-flop circuit 9 becomes "1".
Therefore, the output of inverter 21 becomes "0", and since the most significant bit MSB is "1", AND circuits 19 and 20 are opened.

The flip-flop circuit 7a sets the n bits selected by the selector 11 and the output of the AND circuit 18, and is configured to set the output of the AND circuit 18 and add it to the AND circuit 14. Therefore, the output of the AND circuit 18 is “1”
As a result, the clock signal CLK passes through the AND circuit 14, and the read clock signal RCK is output.

FIG. 4 shows an example of the correspondence between the variable length code information pattern and the code length information, and FIG. 5 shows an example of the operation when a 12-bit configuration of "100000000001" is used as the special code. In FIG. 5, t is the time, A is the input of the multiplexer 4 as the upper bit and the lower bit, that is, the set output of the flip-flop circuit 3 as the upper bit, and the buffer memory 2 as the set output.
B indicates the set output of the flip-flop circuit 9, and the x mark indicates that it is undefined. Further, C indicates a control input of the multiplexer 4, that is, read bit position information. Further, D is the code length information from the code conversion circuit 5, E is the output of the adder circuit 10, and F is the comparator circuit 12.
, and G indicates the output of the flip-flop circuit 7a.

The special code detection circuit 8 detects at least three pieces of 8-bit data sequentially read out from the buffer memory 2.
It has a configuration that detects a special code with a 12-bit configuration by holding the bits of the code once, and at time t1, the upper bit "00010000" and the lower bit "00000010" are added to the multiplexer 4, and at that point A 12-bit special code is detected by the special code detection circuit 8, and the first bit position information "1011" of the special code with the most significant bit MSB set to "1" is set in the flip-flop circuit 9. “1011”
"011" in the figure indicates that the first bit position of the special code is the fourth bit in the 8-bit parallel data from the buffer memory 2.

At that point, if the read bit position information C in the multiplexer 4 is "011" indicating the 4th bit, the code conversion circuit 5 receives 8 bits of "10000000". Also, the most significant bit of the set output of flip-flop circuit 9
Because MSB becomes “1” by special code detection,
The output of the inverter 21 becomes "1" and the AND circuits 19 and 20 are opened. The comparator circuit 12 also contains "011" of n-1 bits excluding the most significant bit MSB of the set output B of the flip-flop circuit 9 and "1" of the output of the AND circuit 19 (the previous output of the inverter 21 was "1"). Flip-flop circuit 2
(This is due to this "1" being set to 4)
is added as the most significant bit MSB, and "1011" of the set output G of the flip-flop circuit 7a
is added and the two match, so the comparison circuit 12
The output F of is "1", and the output of the AND circuit 20 is "1". As a result, the selector 11 selects the set output B of the flip-flop circuit 9 and applies it to the flip-flop circuit 7a, and the flip-flop circuit 7b is set to "1", and the set output is sent to the control circuit 6 as special code detection information. Added.

Further, the output of the AND circuit 20 is "1" and the most significant bit MSB of the set output B of the flip-flop circuit 9 selected by the selector 11 is "1".
Therefore, the output of the AND circuit 18 becomes "1", this "1" is set in the flip-flop circuit 7a, and therefore the read clock signal RCK output from the AND circuit 14 becomes "1" at the timing of the clock signal CLK. becomes.

As mentioned above, at time t1, since no pattern conforming to the variable length code rule is input from the code conversion circuit 5, code length information is not output, and the output E of the addition circuit 10 is not input to the selector 11. Since it is not selected, it becomes unrelated, as shown by the x mark.

At time t2, the next 8 bits of data are read from the buffer memory 2 in response to the read clock signal RCK, so that the special code is not detected by the special code detection circuit 8 at that time, and the set output of the flip-flop circuit 9 is B is an arbitrary value such that the most significant bit MSB is "0". The multiplexer 4 also includes a flip-flop circuit 7a.
The n-1 bit "011" set in is added to the code conversion circuit 5, and "00010011" from the 4th bit is added to the code conversion circuit 5. At this time, the control circuit 6 has received the special code detection information from the flip-flop circuit 7b, so it applies a control signal to the code conversion circuit 5 to forcibly set the output D to "0100" as shown by the * mark. . As a result, the output E of the adder circuit 10 performs the addition of "011" and "100",
“0111” will be output. This output E is applied to the selector 11, and the most significant bit MSB of the set output B of the flip-flop circuit 9 at that time is applied to the selector 11.
Since E is "0", the output E of the adder circuit 10 is selected by the "0" output of the AND circuit 20 and applied to the flip-flop circuit 7a.

Also, since the most significant bit MSB of the output E of the adder circuit 10 selected by the selector 11 is "0",
Since the output of the AND circuit 18 is "0" and therefore the read clock signal RCK output from the AND circuit 14 is "0", no reading from the buffer memory 2 is performed.

At time t3, the input data A of the multiplexer 4 does not change, but the read bit position information C is "111" indicating the 8th bit.
“00110010” is input to the code conversion circuit 5.
Of this input pattern, referring to Figure 4,
Since the 3 bits of “001” are a variable length code pattern, the code conversion circuit 5 converts “0011” into code length information D.
It will be output as Therefore, the adder circuit 10
The output E of is "1010". Most significant bit MSB
becomes "1", the output of the AND circuit 18 becomes "1", this "1" and the output E of the adder circuit 10 selected by the selector 11 are set in the flip-flop circuit 7a, and the clock signal
The read clock signal RCK becomes "1" at the timing of CLK, the next 8 bits of data are read from the buffer memory 2, and the state shifts to the next time t4.

At time t4, since the read bit position information is "010" indicating the third bit, "10010000" from the third bit is added from the multiplexer 4 to the code conversion circuit 5. In the code conversion circuit 5,
“0100” is output as the code length information D of “1001”. The output E of the adder circuit 10 becomes "010", the output E of the adder circuit 10 is set in the flip-flop circuit 7a via the selector 11, and the next read bit position information C is "110", indicating the 7th bit. becomes. In this case, the most significant bit MSB of the set output G of the flip-flop circuit 7a is "0".
Therefore, read clock signal RCK is not output.

At the next time t5, the read bit position information C
indicates the 7th bit, so the code conversion circuit 5 has 7 bits.
“00001011” starting from the bit is input. Code length information D “0110” corresponding to “000010” of the input data is output from the code conversion circuit 5,
Since the addition output E of the addition circuit 10 becomes "1100" and the most significant bit MSB is "1", the read clock signal RCK is output, and the next 8 bits of data are read from the buffer memory 2, and the next time The state shifts to the state shown at t6.

Similarly, at time t8, the special code detection circuit 8 detects the special code, sets the most significant bit MSB to "1", and sets "1011" indicating the leading bit position information in the flip-flop circuit 9. The read bit position information C at that point is “001”
Since this indicates the second bit, "10100000" is added to the code conversion circuit 5. Corresponding to “101” of this input data, code length information D is “0011”
becomes. Further, the output E of the adder circuit 10 becomes "0100". At this point, the special code conversion circuit 8 detects a 12-bit special code, and the flip-flop circuit 9 is set to "1011". Also, in the comparison circuit 12,
“1001” of the output G of the flip-flop circuit 7a
and the set output B of the flip-flop circuit 9 are input, and the flip-flop circuit 7
Since the set output B of a is larger, the comparison output F
becomes “0”. Therefore, the selector 11 selects the output E of the adder circuit 10 and also outputs the read clock signal.
RCK is not output.

In the above case, for example, there is an error in the variable length code "101" due to an error in the transmission path, and the first bit of the special code is decoded as a variable length code. By detecting the special code, the most significant bit MSB of the flip-flop circuit 9 becomes "1", and if the output of the inverter 21 is "0" and the output F of the comparator circuit 12 is "0", the read clock signal is
Since RCK is not output and flip-flop circuit 7b is not set, the next data is input to code conversion circuit 5 in accordance with read bit position information C.

At time t9, the read bit position information C is "100" indicating the 5th bit, so the code conversion circuit 5
“00000000” starting from the 5th bit is input. Also, the set output G of the flip-flop circuit 7a
is "0100" and the set output B of the flip-flop circuit 9 is "1011", so the comparator circuit 12
The output F becomes "1". Therefore, selector 1
1 selects the set output B of the flip-flop circuit 9 and adds it to the flip-flop circuit 7a, and "1" is set in the flip-flop circuit 7b to notify the control circuit 6 of the detection information of the special code. By setting the set output B of the flip-flop circuit 9 to the flip-flop circuit 7a, the read clock signal RCK is output, the next 8 bits of data are read from the buffer memory 2, and the state shifts to the next time t10.

At time t10, the code conversion circuit 5 outputs "0100" indicated by an asterisk (*) as the code length information D in response to a control signal from the control circuit 6. Also, since the read bit position information is "011", the output E of the adder circuit 10 is "0111". Also, at that time, since no special code has been detected, the most significant bit MSB of the set output B of the flip-flop circuit 9 becomes "0". Also, the output E of the adder circuit 10 is selected and set in the flip-flop circuit 7a, but since its most significant bit MSB is "0",
Read clock signal RCK is not output.

In this way, even if there is a bit error in the variable length code and a part of the special code is decoded as a variable length code, the special code can be detected by the special code detection circuit 8. This means that decoding can be correctly started from the beginning of the next variable length code, and the control information that follows the special code can also be correctly detected.

Furthermore, the delay time that determines the operating speed is due to the flip-flop circuit 3, multiplexer 4, code conversion circuit 5, addition circuit 10, selector 11, and AND circuits 18 and 14, and is shorter than the configuration shown in FIG. Since the comparison circuit 12 is not included, the delay time can be shortened accordingly, and when configured with a short key TTL and bipolar ROM, the operating speed can be increased to 12 MHz or more.

Effects of the Invention As explained above, the present invention provides a decoding circuit that sequentially reads data of a predetermined bit length from a buffer memory 2 that receives a variable-length code string at a constant speed, and converts the variable-length code into a fixed-length code. When a special code is detected, the first bit position information and the read bit position information are compared, and if they are the same or the read bit position information is larger, the special code is detected according to the special code detection. It is designed to start decoding the next variable length code,
Even if a part of the special code is decoded as a variable-length code due to a bit error in the variable-length code, it is possible to correctly decode the variable-length code from the next special code, and the read bit position information can be transferred to the multiplexer. Since the delay time of the path added to step 4 can be shortened, there is an advantage that high-speed operation is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional variable length code decoding circuit, FIG. 2 is a block diagram of a basic circuit of an embodiment of the present invention, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a block diagram of a conventional variable length code decoding circuit. 5 is an explanatory diagram of an example of the relationship between a variable length code pattern and code length information, and FIG. 5 is an explanatory diagram of the operation of the embodiment of the present invention. 1 is an input terminal, 2 is a buffer memory, 3 is a flip-flop circuit, 4 is a multiplexer, 5 is a code conversion circuit, 6 is a control circuit, 7a, 7b are flip-flop circuits, 8 is a special code detection circuit, 9 is special code detection information and a flip-flop circuit for setting the first bit position information; 10 is an adder circuit for adding the read bit position information and the code length information; 11
is a selector, 12 is a comparison circuit, 14, 18, 1
9 and 20 are AND circuits, 21 is an inverter, 22
23 is a buffer memory read stop circuit, and 24 is a flip-flop circuit.

Claims (1)

[Claims] 1. A buffer memory 2 that receives constant speed code string data in which a control signal and a plurality of variable length codes are inserted between special codes of a predetermined bit pattern; A multiplexer 4 that sequentially reads data and outputs data of a predetermined bit length from a bit position according to the read bit position information, inputs the data from the multiplexer, identifies a variable length code according to the variable length code rule, and converts the data to the variable length code. a code conversion circuit 5 that outputs code length information of the code; an addition circuit 10 that adds the code length information from the code conversion circuit and the read bit position information to obtain next read bit position information; and detects the special code. a special code detection circuit 8 which outputs the first bit position information from the special code detection circuit; a comparison circuit 12 which compares the first bit position information from the special code detection circuit with the read bit position information used in the multiplexer; A selector that uses the first bit position information as the next read bit position information when there is a comparison match or the first bit position information is smaller, and otherwise uses the output of the adder circuit as the next read bit position information. 11. When the special code is detected and the selector is controlled by the output of the comparison circuit to select the read bit position information, the buffer memory is read out.