JPS6014456A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6014456A
JPS6014456A JP58121644A JP12164483A JPS6014456A JP S6014456 A JPS6014456 A JP S6014456A JP 58121644 A JP58121644 A JP 58121644A JP 12164483 A JP12164483 A JP 12164483A JP S6014456 A JPS6014456 A JP S6014456A
Authority
JP
Japan
Prior art keywords
wiring
base
semiconductor device
film
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58121644A
Other languages
Japanese (ja)
Other versions
JPH0481331B2 (en
Inventor
Kanji Otsuka
寛治 大塚
Takayuki Okinaga
隆幸 沖永
Toshiro Kuroda
俊郎 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Narumi China Corp
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Narumi China Corp
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Narumi China Corp, Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Narumi China Corp
Priority to JP58121644A priority Critical patent/JPS6014456A/en
Publication of JPS6014456A publication Critical patent/JPS6014456A/en
Publication of JPH0481331B2 publication Critical patent/JPH0481331B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE:To micro-miniaturize a wiring while executing the wiring and pellet bonding at low cost by forming the wiring on a base for a package by a thin- film wiring and using a base metal, such as aluminum, copper, etc. and a resin material as the wiring and a bonding material. CONSTITUTION:A base 1 constituting a package substrate as a wiring substrate is formed in a sintered body, etc. mainly comprising ceramics or electrical insulating SiC, and lead pins 5 for external terminals made of a 42 alloy, etc. are connected and fixed to internal wirings 2 through plating layers 3 in Ni, etc. and a solder material 4 such as Ag. Thin-film wirings 6 consisting of an evaporated film of Al or Cu are formed by using mask evaporation or photolithography technique. An Si semiconductor pellet 7 is bonded on the thin-film wiring 6A by a joining material 8 such as polyimide resin, connected to the thin-film wirings 6 by Al wires 9, and sealed in an airtight manner by a cap 11. The wirings can be micro-miniaturized and mounted with high density more than wirings through Au metallizing.

Description

【発明の詳細な説明】 ［技術分野］ 本発明は半導体装置、さらには高密度実装が要求される
半導体装置に適用して特に効果のある技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is particularly effective when applied to semiconductor devices, and more particularly to semiconductor devices that require high-density packaging.

［背景技術］ たとえばセラミック等で作られたパッケージに半導体ペ
レットを取りイ」ける場合、パッケージ基板のベレット
取イ１面に形成した金めつきと半うタ体ペレットのシリ
コン材料との金（Ａｕ）−シリコン（Ｓｉ）共晶構造に
よりベレット付けを行っている（日本マイクロエレクト
ロニ多ス協会編ＦＩＣ化実さ一″Ｈ３術Ｊ１００Ｐ）。[Background Art] For example, when a semiconductor pellet is placed in a package made of ceramic or the like, gold (Au) is formed between the gold plating formed on one side of the pellet hole of the package substrate and the silicon material of the semi-cylindrical pellet. ) - Bereting is performed using a silicon (Si) eutectic structure (Japan Microelectronics Association, FIC Kajitsu-ichi, H3 Jutsu J100P).

ところが、このＡｕ−３ｉ共品によるペレット付けを行
う場合、金めつきが良好に行われていないと、Ａｕ−３
ｉの濡れが悪くなり、ペレノ１〜付けの信頼性が低下し
てしまう。However, when attaching pellets using this Au-3i product, if the gold plating is not done well, the Au-3
The wettability of I becomes poor, and the reliability of attaching Pereno 1 to 1 decreases.

さらに、パッケージのベース上の表面配線として金メタ
ライズ層の如き圧膜配線を使用することが考えられる。Furthermore, it is conceivable to use thin film wiring such as a gold metallized layer as the surface wiring on the base of the package.

前記いずれの場合にも金を用いているため、コストが非
常に高くなるという重大な問題点がある。Since gold is used in both of the above cases, there is a serious problem in that the cost is extremely high.

さらに、また、ベース上の配線として金メタライズＮを
使用した場合、金膜の厚みが大きいので、高密度実装の
可能な微細配線を得ることに限度がある等の問題がある
。Furthermore, when gold metallized N is used as wiring on the base, there are problems such as there being a limit to obtaining fine wiring that can be mounted at high density because the gold film is thick.

［発明の目的］ 本発明の目的は、パンケージのベース」二の配線を微細
化でき、高密度実装を可能にする半導体装置を提供する
ことにある。[Object of the Invention] An object of the present invention is to provide a semiconductor device in which wiring at the base of a pancage can be miniaturized and high-density packaging is possible.

本発明の他の目的は、ベース上の配線およびペレットボ
ンディングを低コストで行うことのできる半導体装置を
提供することにある。Another object of the present invention is to provide a semiconductor device in which wiring on a base and pellet bonding can be performed at low cost.

本発明のさらに他の目的は、ベース上の配線として電気
抵抗の低い安価な卑金兄を使用した際のペレット付けを
容易にすることにある。Still another object of the present invention is to facilitate pellet attachment when using cheap base metal with low electrical resistance as the wiring on the base.

本発明のさらに伯の目的は、ペレット付は材料を考慮し
たパッケージのキャップの封止材を使用することにある
。A further object of the present invention is to use a sealing material for a package cap that takes into consideration the material used for attaching pellets.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

「発明の概要」 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。"Summary of the Invention" A brief summary of typical inventions disclosed in this application is as follows.

すなわち、配線基板としてのパッケージのベース上の配
線を薄膜配線で形成し、しかもその薄膜配線材料および
ペレットボンディング材料としてそれぞれアルミニウム
や銅等の安価な卑金属および樹脂材料を使用することに
より、前記目的を達成するものである。That is, by forming the wiring on the base of the package as a wiring board with thin film wiring, and using inexpensive base metals such as aluminum and copper and resin materials as the thin film wiring material and pellet bonding material, respectively, the above objective can be achieved. It is something to be achieved.

［実施例１］ 第１図は本発明の実施例１である半導体装置の断面図で
ある。[Example 1] FIG. 1 is a sectional view of a semiconductor device which is Example 1 of the present invention.

この実施例１において、配線基板としてのパッケージ基
板を構成するベース１はたとえばセラミックあるいは特
開昭５６−６６０８６号公報、同５７−２５９１号公報
で開示される電気絶縁性のシリコンカーバイ１〜（Ｓｉ
Ｃ）を主成分とする焼結体等で作られている。このベー
ス】は複数層の積層構造よりなり、その内部には内部配
線２が表面側から裏面側まで形成されている。In this embodiment 1, the base 1 constituting the package substrate as a wiring board is made of, for example, ceramic or electrically insulating silicon carbide 1 to ( Si
It is made of a sintered body etc. whose main component is C). This base has a laminated structure of multiple layers, and internal wiring 2 is formed inside thereof from the front side to the back side.

前記内部配線２の裏面側には、タングステン（Ｗ）−ニ
ッケル（Ｎ１）等のめっき層３および銀（八ｇ）等のろ
・う材４を介して、４２７０イ等の外部端子用のリード
ピン５がパッケージのベースの裏面から垂直方向に接続
固定されている。Lead pins for external terminals such as 4270I are connected to the back side of the internal wiring 2 through a plating layer 3 such as tungsten (W)-nickel (N1) and a filler material 4 such as silver (8g). 5 is connected and fixed in the vertical direction from the back side of the base of the package.

一方、前記ベース１の表面側には、アルミニウム（Ａ１
）または多口（Ｃｕ）の蒸着膜よりなる員Ｖ股配線６が
表面配線としてたとえばマスク蒸着もしくはホトリソグ
ラフィ技術を用いて形成されている。この膜薄配線６は
内部配線２のいずれかと導電接続されている。ホトリソ
グラフィ技術は前述のシリコンカーバイト焼結体の表面
を鏡面研摩している場合、特に好適である。On the other hand, aluminum (A1
) or a multilayer (Cu) vapor-deposited film is formed as a surface wiring using, for example, mask vapor deposition or photolithography technology. This thin film wiring 6 is conductively connected to any of the internal wirings 2. The photolithography technique is particularly suitable when the surface of the silicon carbide sintered body mentioned above is mirror-polished.

前記ＨＶ　ｂ配線６はベース１の表面中央部のイレン１
−ボンディング位置にも被着されており、この表面中央
部の薄膜配線６Ａの上には、たとえばシリコン（Ｓｉ）
よりなる半導体ペレット７がペレットボンディング用の
接合祠８によりボンディングされている。この接合月８
は高耐熱性の樹脂材料であるポリイミド樹脂等で作られ
ている。The HV b wiring 6 is located at the center of the surface of the base 1.
- It is also deposited at the bonding position, and on the thin film wiring 6A at the center of the surface, for example, silicon (Si) is deposited.
Semiconductor pellets 7 made of the following are bonded by a bonding hole 8 for pellet bonding. This conjunction month 8
is made of polyimide resin, which is a highly heat-resistant resin material.

前記ペレット７のポンディングパッドはたとえばアルミ
ニウムよりなるワイヤ９で″Ａｒｉ膜配線６に電気的に
接続されている。The bonding pad of the pellet 7 is electrically connected to the ``Ar'' film wiring 6 by a wire 9 made of aluminum, for example.

さらに、前記ペレット７、ワイヤ９等は封止材１０でキ
ャップ１１をベース１の周辺部上に接合、’；Ｅｌ　定
１−ることにより気密封止されている。Further, the pellet 7, wire 9, etc. are hermetically sealed by bonding a cap 11 onto the peripheral portion of the base 1 using a sealing material 10.

この封止材１０として、本実施例では低融点ガラスが用
いられている。このような低融点ガラスの溶融封止温度
は約４１０〜４５０℃であるが、本実施例でペレットボ
ンディング用に用いられている接合＋Ａ８としてのポリ
イミド樹脂は約４６０°Ｃの耐熱性を有するので、封止
温度に十分耐えることができる。As this sealing material 10, low melting point glass is used in this embodiment. The melting and sealing temperature of such low-melting point glass is about 410 to 450°C, but the polyimide resin used as bonding + A8 for pellet bonding in this example has a heat resistance of about 460°C. , can sufficiently withstand the sealing temperature.

前記キャップ１１はベース１と同様に、たとえばセラミ
ックあるいは前述のシリコンカーバイトを主成分とする
月料で作ることができる。The cap 11, like the base 1, can be made of, for example, ceramic or the aforementioned silicon carbide-based material.

本実施例においては、ベース１上の表面配線としてアル
ミニウムまたは銅の范着眉等の薄膜配線６が形成されて
いるので、Ａｕメタライズによって配線を形成する場合
に較べ配線の微細化、ひいては高密度実装化が可能とな
る。In this embodiment, thin film wiring 6 such as aluminum or copper wire is formed as the surface wiring on the base 1, which results in finer wiring and higher density than when wiring is formed by Au metallization. Implementation becomes possible.

また、本実施例では、表面配線およびベレットボンディ
ング用のＪＡ料として高価な貴金属、特に金が全く使用
されていないので、大巾に低コスト化を図ることができ
る。Furthermore, in this embodiment, expensive noble metals, particularly gold, are not used at all as the JA material for surface wiring and bullet bonding, so it is possible to significantly reduce costs.

また、配線として形成した金属層をペレット付けに用い
るのが通常であるが、アルミニウムや銅はそのままでは
ベレット付りに用いることはできない。この点、本実施
例によれば容易にペレットイ」けができるうえ、封止温
度まで考慮しているので信頼性を高めることができる。Further, although it is usual to use a metal layer formed as a wiring for attaching pellets, aluminum or copper cannot be used as is for attaching pellets. In this regard, according to this embodiment, not only can the pellets be easily damaged, but also the sealing temperature is taken into consideration, so reliability can be improved.

［実施例２］ 第２図は本発明の実施例２である半導体装置の断面図で
ある。[Example 2] FIG. 2 is a sectional view of a semiconductor device which is Example 2 of the present invention.

この実施例２では、キャンプ封止用の封止材として、た
とえばエポキシ樹脂またはシリコーン樹脂の如き樹脂材
料が使用されている。このような樹脂材料の封止＋８１
０　Ａの場合には、封止温度がたとえば約２００℃程度
であるので、実施例１の低融点ガラスによる封止の場合
よりも低温で封止できる。In this second embodiment, a resin material such as epoxy resin or silicone resin is used as the sealing material for camp sealing. Sealing of such resin materials +81
In the case of 0 A, the sealing temperature is, for example, about 200° C., so sealing can be performed at a lower temperature than in the case of sealing with low melting point glass in Example 1.

ソノタメ、本実施例では、ペレットボンディング用の接
合祠としても、ポリイミド樹脂の他に、たとえばシリコ
ーン樹脂（耐熱温度−約２５０℃）、Ａｇ人りエポキシ
樹脂（耐熱温度−３００℃）等よりなる接合材８Ａが用
いられている。In this embodiment, in addition to polyimide resin, bonding materials such as silicone resin (heat resistant temperature - about 250°C), Ag-filled epoxy resin (heat resistant temperature - 300°C), etc. are used as the bonding shrine for pellet bonding. Material 8A is used.

この実施例の場合にも、ベース１上の表面配線が７ｖ欣
配線として形成されているため、Ａｕメタライズによっ
て配線を形成した場合に較べ、微細配線が可能である。In this embodiment as well, since the surface wiring on the base 1 is formed as a 7V wiring, finer wiring is possible than in the case where the wiring is formed by Au metallization.

また、配線およびペレットボンディング用の材料として
アルミニウム、銅等の卑金属および樹脂材料をそれぞれ
用いているため、コストを低減することができる他、実
施例１と同様の効果が得られる。Further, since base metals such as aluminum and copper and resin materials are used as materials for wiring and pellet bonding, costs can be reduced and the same effects as in Example 1 can be obtained.

［効果］ （１）、パッケージの−、−ス上の配線として電気抵抗
の低い卑金属の薄膜配線を形成しているので、高速な半
導体装置を実現できる。[Effects] (1) Since thin film wiring of base metal with low electrical resistance is formed as wiring on the - and - terminals of the package, a high-speed semiconductor device can be realized.

（２）、配線およびペレットボンディング用の材料とし
て高価な貴金属、特に金を用いていないので、コストの
低減を図ることができる。(2) Since expensive noble metals, especially gold, are not used as materials for wiring and pellet bonding, costs can be reduced.

（３）、パッケージのベース上の配線として電気抵抗の
低い卑金属の薄膜配線をマスク蒸着あるいはボトリソグ
ラフィ技術により形成しているので、配線の微細化が可
能であり、高密度実装を実現できる。(3) As the wiring on the base of the package is formed using a thin film wiring made of a base metal with low electrical resistance by mask vapor deposition or bottom lithography technology, it is possible to miniaturize the wiring and realize high-density packaging.

（４）、ペレットボンディング用の拐料として樹脂材料
を用いているので、ペレット付けに使用するのが困難な
銅、アルミニウム等をベレット付けに使用せずに済み、
ベレツト付けを容易にできる。(4) Since a resin material is used as a bonding material for pellet bonding, it is not necessary to use copper, aluminum, etc., which are difficult to use for pellet bonding, for pellet bonding.
Berets can be attached easily.

（５）、ペレット伺げに使用される樹脂材料の耐熱温度
を考慮して、それよりも低い封止温度のパッケージのキ
ャンプの封止材を使用しているので、確実なＩＪ止がで
き、また、ベレット付けの信頼性を高めることができる
。(5) Considering the heat resistance temperature of the resin material used for the pellet cover, we use a package sealing material with a lower sealing temperature than that, allowing for reliable IJ sealing. , the reliability of beret attachment can be increased.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえば、ペレットボンディング用の樹脂材料は、好ま
しくは、熱伝導性を良くする材料の粉末たとえばｔＪｌ
を添加したものを用いることができる。For example, the resin material for pellet bonding is preferably a powder of a material that improves thermal conductivity, such as tJl
can be used.

また、ベレ７＋・ボンディング位置におけるベース上の
Ｍ膜配線ば省略することができる。Furthermore, the M film wiring on the base at the verge 7+ bonding position can be omitted.

し利用分野」 以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である１　（ｌ！ｉｌのベ
レノ１−を有する半導体装置に適用した場合について説
明したが、それに限定されるものではなく、たとえば、
複数個のベレットよりなるマルヂチノプ型の半導体装置
等にも適用できる。In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to a semiconductor device having Vereno 1-, which is the background of the invention, but the invention is not limited to this. For example,
It can also be applied to a Marditinop-type semiconductor device made of a plurality of pellets.

本発明は少なくとも配線基板上に電気抵抗の小さいキ金
属の薄膜配線を有し、樹脂月料でべＩ／ノ１−を固着す
る半９１１体装置であれば適用できる。The present invention can be applied to any semi-911 device that has at least a metal thin film wiring with low electrical resistance on a wiring board and has a base plate (I/NO) fixed with a resin layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例１である半導体装置の断面図、 第２図は本発明の実施例２である半導体装置の断面図で
ある。 １・・・バノゲージのベース、２・・・内部配線、３・
・・めっき層、４・・・ろう材、５・・・リードピン、
６．６Δ　・・薄膜配線、７・・・ヘレソ１−１８．８
Δ・・・ペレットボンディング用の接合材、９・・・ワ
イヤ、１０，１０Δ・・・封止材。1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. 1...Bano gauge base, 2...Internal wiring, 3.
... Plating layer, 4... Brazing metal, 5... Lead pin,
6.6Δ...Thin film wiring, 7...Hereso 1-18.8
Δ... Bonding material for pellet bonding, 9... Wire, 10,10Δ... Sealing material.

Claims (1)

【特許請求の範囲】 ■、パッケージのベースと、前記ベースの主表面の一部
に耐熱性を有よる樹脂材料で固着されたペレットと、前
記ベースの主表面の少なくとも他の部分に前記ペレット
に対向して形成された電気抵抗の低い卑金属の複数の薄
膜と、前記ペレノ１−を封止するために前記ベースに耐
熱性を有する封止材で固着されたパッケージのキャンプ
とを有することを特徴とする半導体装置。 ２、前記薄膜がアルミニウムの蒸着薄膜よりなることを
特徴とする特許請求の範囲第１項記載の半導体装置。 ３、前記薄膜が銅の蒸着薄膜よりなることを特徴とする
特許請求の範囲第１項記載の半導体装置。 ４、前記封止材が低融点ガラスよりなり、前記樹脂材料
がポリイミド樹脂よりなることを特徴とする特許請求の
範囲第１項ないし第３項のいずれかに記載の半導体装置
。 ５、前記封止材が樹脂材料よりなり、前記樹脂材料がポ
リイミド樹脂、エポキシ樹脂またはシリコーン樹脂より
なることを特徴とする特許請求の範囲第１項ないし第３
項のいずれかに記載の半導体装置。[Claims] (1) A base of the package, a pellet fixed to a part of the main surface of the base with a heat-resistant resin material, and a pellet fixed to at least another part of the main surface of the base. It is characterized by having a plurality of thin films of base metal with low electrical resistance formed to face each other, and a package camp fixed to the base with a heat-resistant sealing material to seal the pereno 1-. semiconductor device. 2. The semiconductor device according to claim 1, wherein the thin film is a vapor-deposited aluminum film. 3. The semiconductor device according to claim 1, wherein the thin film is a vapor-deposited copper thin film. 4. The semiconductor device according to any one of claims 1 to 3, wherein the sealing material is made of low melting point glass, and the resin material is made of polyimide resin. 5. Claims 1 to 3, wherein the sealing material is made of a resin material, and the resin material is made of polyimide resin, epoxy resin, or silicone resin.
3. The semiconductor device according to any one of the items.
JP58121644A 1983-07-06 1983-07-06 Semiconductor device Granted JPS6014456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58121644A JPS6014456A (en) 1983-07-06 1983-07-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58121644A JPS6014456A (en) 1983-07-06 1983-07-06 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6014456A true JPS6014456A (en) 1985-01-25
JPH0481331B2 JPH0481331B2 (en) 1992-12-22

Family

ID=14816356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58121644A Granted JPS6014456A (en) 1983-07-06 1983-07-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6014456A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101652482B1 (en) * 2015-05-12 2016-08-30 메디컬아이피 주식회사 Transparent product manufacturing method and transparent product by the method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5165568A (en) * 1974-12-04 1976-06-07 Hitachi Ltd
JPS558057A (en) * 1978-07-04 1980-01-21 Hitachi Ltd Semiconductor
JPS56155555A (en) * 1980-05-06 1981-12-01 Seiko Epson Corp Semiconductor device
JPS5795952U (en) * 1980-12-03 1982-06-12
JPS5848944A (en) * 1981-09-18 1983-03-23 Hitachi Ltd Airtight sealing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5165568A (en) * 1974-12-04 1976-06-07 Hitachi Ltd
JPS558057A (en) * 1978-07-04 1980-01-21 Hitachi Ltd Semiconductor
JPS56155555A (en) * 1980-05-06 1981-12-01 Seiko Epson Corp Semiconductor device
JPS5795952U (en) * 1980-12-03 1982-06-12
JPS5848944A (en) * 1981-09-18 1983-03-23 Hitachi Ltd Airtight sealing method

Also Published As

Publication number Publication date
JPH0481331B2 (en) 1992-12-22

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