JPS6014530A - Delay equalizing system - Google Patents

Abstract

PURPOSE:To correct economically the waveform distortion of a demodulated output to reduce the reception error rate by controlling the delay characteristics in a base band in accordance with the amplitude of an input signal to perform delay equalization in the FM system. CONSTITUTION:An amplitude characteristics A and a delay characteristics tau of an IF filter 2 are as shown in figure. An output signal waveform S' of an FM detector 4 is delayed for a transmission-side transmission signal waveform S by a delay quantity tau'. With respect to a delay quantity tauv' in the case where the amplitude of the waveform S' is V, a delay quantity tauv of the filter 2 corresponding to a frequency fv for the output of the amplitude V is dominant. That is, the waveform distortion of the signal waveform S' is determined almost by the amplitude. Consequently, for the purpose of equalizing the waveform distortion of the waveform S', it is sufficient if the same delay quantity as the delay quantity tau' is cancelled. The delay quantity of a delay circuit 5 is set in accordance with the amplitude so that it is tau0-tau' (tau0 is a fixed value). Thus, since an output waveform S'' of the delay circuit 5 is delayed for the waveform S by tau'+ (tau0-tau')=tau0, the distortion is eliminated. A delay control part 8 detects the amplitude of the waveform S' to control the delay quantity of the delay circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a delay equalization method for a digital signal frequency modulation method (hereinafter referred to as FM) transceiver.

In particular, it relates to delay equalization methods for narrowband FM transceivers.

[Description of prior art]

Conventionally, when a digital signal is transmitted in a narrow band using an FM modulation method, code amount interference in the demodulated output caused by the delay characteristics of the intermediate frequency filter (hereinafter referred to as IP filter) of the receiver is detected by signal identification on the receiver side. Sometimes it becomes a big problem. However, when using the transversal method as an automatic equalization technique, for example, a large number of multipliers are required, which makes the circuit extremely complex and expensive. In addition, there is a limit to improving the characteristics of the engineered F filter itself; if the amplitude characteristics are good, the delay characteristics will deteriorate, and conversely, if the delay characteristics are improved, the phase characteristics will deteriorate. There were drawbacks.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and to provide a delay equalization method for delay-equalizing nonlinear distortion in the demodulated output of a receiver that occurs due to the delay characteristics of an engineered F filter.

[Features of the invention]

The present invention provides a delay equalization method for an FM transceiver.
In order to correct the non-linear distortion of the demodulated output of the receiver caused by the delay characteristics of the filter, it is constructed with a delay equalization means that controls the delay characteristics from the amplitude trap of the input signal in the baseband of the transmitter or receiver. It is characterized by The delay equalization circuit is preferably an analog delay circuit or an active phase shift circuit comprising an analog delay element controlled by a high-speed clock, a resistor, a capacitor, and an operational amplifier.

[Explanation based on examples]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a delay equalization circuit according to an embodiment of the present invention. An FM signal is input to a radio receiver 1, an IF filter 2 is connected to the output of the radio receiver 1, and an FM signal is input to the IF filter 2. A limiter amplifier 3 is connected to the output of the mechanical F filter 2. Limiter amplifier 3
An FM detector 4 is connected to the output of the FM detector 4. FM detector 4
A delay circuit 5 is connected to the output of the delay circuit 5, and a baseband signal is input to the delay circuit 5. A baseband filter 6 is connected to the output of the delay circuit 5.

An identification circuit 7 is connected to the output of the baseband filter 6, and an identified digital signal is sent out from the identification circuit 7. Further, a delay control section 8 is connected to the output of the FM detector 4, which controls the amount of delay based on the amplitude of the baseband signal output. The output of the delay control section 8 includes a delay circuit 5.
are connected and controlled. FIG. 4 is a block diagram of a delay equalizer according to an embodiment of the present invention. Baseband input signal D
The EL-AY circuit N is connected to the delay circuit 5 and the analog-to-digital converter 9 of the delay control section 8. A read-only memory 10 is connected to the output of the analog-to-digital converter 9. A digital-to-analog converter 11 is connected to the output of the read-only memory 10.

An oscillator 12 is connected to the output of the digital-to-analog converter 11.
is connected. A delay circuit 5 is connected to the output of the oscillator 12, and a signal whose waveform distortion has been corrected is sent out from the delay circuit 5. The delay circuit 5 uses an analog delay element that operates with a high-speed clock.

FIG. 5 is a circuit diagram of a delay equalizer according to another embodiment of the present invention.

Baseband input signal DELAY IN is connected to capacitor C
and is input to resistor R1. A nonlinear circuit 14 is connected to the capacitor C. The nonlinear circuit 14 includes a resistor R3, a diode X, and a diode X2 connected in parallel. One terminal of the resistor R3 is connected to a capacitor C, and the other terminal is grounded. The "+" input terminal of the operational amplifier 13 is connected to the connection point between the capacitor C and the resistor R3. The "-" input terminal of the operational amplifier 13 is connected to the resistor R1. The operational amplifier 13 outputs a signal DELAY OUT whose waveform distortion has been corrected. Operational amplifier 1
The output of 3 is connected to the "-" of operational amplifier 13 via resistor R2.
It is connected to the input terminal, and a portion of the signal DBTJAY OUT is fed back.

The operation of such a delay equalizer is shown in Figures 1 and 2.
This will be explained using FIG. 5, FIG. 4, and FIG. FIG. 2 is an amplitude and delay characteristic diagram of the engineered F filter in FIG. 1. FIG. 3 is a waveform diagram of the transmitting side modulator input signal, an FM detector output signal waveform, and a delay circuit output signal waveform diagram in FIG. 1. An example of the characteristics of the engineered F filter 2 shown in FIG. 1 is shown in FIG. A represents the amplitude characteristic, and τ represents the delay characteristic.

That is, the receiving 17 frequency is the center frequency gQ f. In the range close to K, the output of the F filter 2 is at a sufficient level,
Although the delay amount τ is small, the receiving 17 frequency is the center frequency f.

As I get further away from I? The output level of filter 2 has become small, and the delay 1τ has become large. FIG. 3 shows an example of detecting the FM signal that has passed through this finely tuned F filter 2.

When the received IF frequency changes between -fM and +1M, the output of the 7M detector 4 outputs a voltage that changes between -1 and -1. Let B be the input signal waveform (hereinafter referred to as the transmission signal waveform) of the transmitting side FM modulator (not shown).

The output signal waveform S of the 7M detector 4 with respect to the transmitted signal waveform
′ is delayed by the delay amount τ′. The delay amount τ of the 1F filter 2 has the greatest influence on the delay amount τ'. Here, if the amplitude of the output signal waveform S' of the 7M detector 4 is V, the delay amount at this time is the delay amount τ7 of the F filter 2 corresponding to the frequency fv when outputting the amplitude V. Become dominant. From this, it can be seen that when the amplitude of the output signal waveform S' of the 7M detector 4 is .tau.V, .tau.V' is .tau.V. That is, the waveform distortion in the output signal waveform S' of the 7M detector 4 is determined mostly by the amplitude. This means that in order to equalize the waveform distortion of the output signal waveform S' of the 7M detector 4, it is only necessary to cancel the same amount of delay as the delay amount τ' of the output signal waveform S'. do.

The delay ft of the delay circuit 5 in FIG. 1 depends on the amplitude:
τ. −τ′. Here, τ0 is a constant value. Therefore, the waveform S after passing through the delay circuit 5 is τ'+(τ.-τ')=
τ.

Distortion is removed because the waveform is delayed by . Regarding FIG. 1, the delay controller 8 controls the output signal waveform S of the 7M detector 4.
A delay control unit 8 detects the amplitude of the signal ` and controls the amount of delay of the delay circuit 5. The delay circuit 5 and delay control section 8 will be explained below.

In FIG. 4, the delay circuit 5 is B B D (Bu
cketBrigade Device) or CO
An analog delay element such as D (Charge-DoupledDeviceθ) is used.

Further, the delay control section 8 for determining the amount of delay is configured as follows. The delayed input signal DmLAY IN is converted into a digital signal by the analog/digital converter 9, the contents of the read-only memory (hereinafter referred to as ROM) 10 are selected, and the digital/analog converter 11 is converted according to the contents of ROMi0 at this time. A control voltage is generated to variably control the frequency fH of the oscillator 12. Frequency f at this time
The amount of delay of the delay circuit 5 is determined by E. ROM
The contents of 10 indicate that the delay amount of the delay circuit 5 is τ corresponding to the amplitude of the delayed input signal DELAY IN. The information is −τ′.

Here, τ' is the delay amount of the signal DELAY IN and I
This corresponds to the delay amount τ of the F filter. In this method,
By finely setting the contents of ROM10, it is possible to sufficiently cancel out the code amount interference caused by the delay of the IF filter.

In FIG. 5, the delay circuit 5 and the delay control s of FIG.
The portion corresponding to 8 is made up of one circuit. Fifth
The circuit shown in the figure is a first-order phase shift circuit, and the diode xj
,
r), and is given by θ--tan (ωCr) as a delay phase amount. When cr is sufficiently large, r is a function of the amplitude of the delayed input signal DELAY IH, and becomes a small value where the amplitude is high. Therefore, for a waveform in which the amount of delay increases with amplitude, such as the waveform in Figure 5,
Conversely, r decreases with the amplitude, and as a result, the delay phase amount θ also decreases, so that the delay characteristics of the engineered F filter can be corrected.

In the specific example shown in FIG. 5, the delay characteristics in the phase shift circuit are approximate ones that utilize nonlinear distortion caused by diodes.
Although it is not possible to completely cancel the baseband waveform distortion caused by the delay of the 1F filter, it is possible to reduce the deterioration of the error rate of received data with the simplest configuration.

The example described so far is a case where distortion is corrected on the receiving side, but the same can be said even if the transmitting side is corrected in advance so that it has a delay characteristic opposite to that of the 1F filter. In this case, the delay circuit 5 and its control means 8 may be inserted on the input side of the modulator.

〔Effect of the invention〕

As explained above, the present invention economically reduces the waveform distortion in the demodulated output caused by the delay characteristics of the engineered F filter by controlling the delay characteristics manually using the amplitude of each signal in the 1-base node and performing delay equalization. This correction has the excellent effect of reducing the deterioration of the reception error rate of digital signals in narrowband transmission.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a delay equalization circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing the amplitude and delay characteristics of the filter in FIG. 1. FIG. 3 is a waveform diagram of the transmitting side modulator signal waveform, an FM detector output signal waveform diagram, and a delay circuit output signal waveform diagram in FIG. 1. FIG. 4 is a block diagram of a delay equalizer according to an embodiment of the present invention. FIG. 5 is a block diagram of a delay equalizer according to another embodiment of the present invention. 1... Radio receiver, 2... Engineering F filter, 3...
Limiter amplifier, 4...FM detector, 5...Delay circuit, 6...Baseband filter, 7...Identification circuit, 8...Delay control section, 9...Analog-digital converter , 10... Read only memory (ROM), 11
...Digital-to-analog converter, 12...Transmitter,
13... operational amplifier, 14... nonlinear circuit. Patent applicant: NEC Corporation Representative Patent attorney: Naotaka Ide

Claims (8)

[Claims] (1) A receiver that receives an FM modulated signal and outputs an intermediate frequency signal, an intermediate frequency filter that generates F waves from this intermediate frequency signal, and an FM detector that detects this intermediate frequency signal and outputs a baseband signal. and a delay means for controlling the amount of delay of the baseband signal in accordance with the amplitude of the baseband signal, the delay means correcting distortion of the FM demodulated output caused by the delay characteristic of the intermediate frequency filter. A delay equalization method is constructed as follows. (2) The delay means is constituted by an analog delay circuit that delays the parse band signal, and a delay control section that controls the amount of delay of the analog delay circuit in accordance with the amplitude of the baseband signal. The delay equalization method described in range (1). (3) The analog delay circuit is an active phase shift circuit including a resistor, a capacitor, and an operational amplifier, and the delay controller is configured to change the value of the resistor in accordance with the amplitude of the baseband signal. A delay equalization scheme according to claim (2) as constructed. (4) The analog delay circuit is an analog delay element that operates with a high-speed clock, and the delay control section is configured to generate the high-speed clock in accordance with the amplitude of the baseband signal. Delay equalization method described in (2). (5) a transmitter that modulates and transmits a signal; a delay unit that controls the amount of delay of the baseband signal in accordance with the amplitude of the baseband signal that is the FM modulation input signal of the transmitter; and the FM A receiver that receives a modulated signal and outputs an intermediate frequency signal, and an intermediate frequency filter that outputs an R wave of this intermediate frequency signal, and the delay means eliminates distortion of the FM demodulated output caused by the delay characteristics of the intermediate frequency filter. A delay equalization scheme configured to compensate for. (6) The delay means includes an analog delay circuit that delays a baseband signal that is an FM modulation input signal of the transmitter, and a delay control section that controls the amount of delay of this analog delay circuit in accordance with the amplitude of the input signal. A delay equalization method according to claim (5) constituted by: (7) The analog delay circuit is an active phase shift circuit including a resistor, a capacitor, and an operational amplifier, and the delay controller is configured to change the value of the resistor in accordance with the amplitude of the baseband signal. A delay equalization scheme according to claim (6) as constructed. (8) The analog delay circuit is an analog delay element that operates with a high-speed clock, and the delay control section is configured to generate the high-speed clock in accordance with the amplitude of the baseband signal. (6) Delay! J! ; Equalization method.