JPS60159960A - Communicating system between devices connected onto bus - Google Patents

Abstract

PURPOSE:To execute efficiently a data transfer between optional devices without informing and decoding a device number by each device, when transferring a data between each device, by providing plural separate device signal lines and a common signal line. CONSTITUTION:Separate device signal lines 12 send separately a bus use request to a bus control device 30 from a processing device 20, and separate device signal lines 13 send separately a bus use permission from the device 30 to the device 20 which has generated the bus use request. Also, a common signal line 14 sends a signal for informing in advance a receiving time of a data to the device 20 of a receiving side, when transferring a data between the device 20(i) and 20(j), or to the device 20 from the device 30. Transmission and reception of a data between the device 20 and 30, and between the device 20(i) and 20(j) are executed optionally and selectively through a bus 10 constituted of these signal lines, by which each device is controlled so as to communicate to only a main storage 40 through the device 30 at all times. That is to say, each device can transfer a data efficiently without executing information, etc. of a device number.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention provides information on a bus system in which a plurality of processing devices and a bus control device that determines the right to use the bus for each of these processing devices are connected on a bus. The present invention relates to a communication method between devices connected on a bus used in a processing system.

[Technical background of the invention and its problems]

In an information processing system, as a means of interconnecting each device such as a central processing unit, input/output processing unit, and main storage device, each of these devices is placed on the same bus, and the bus There is a so-called bus method in which data is transferred between devices by selectively using the bus. There have been many types of bus systems of this type.For example, from the perspective of bus usage right acquisition control, each device has a bus contention circuit for acquiring the bus usage right. However, if you classify the bus from the perspective of bus usage time, once you start using a pass, there will be idle time until the end of one command. There are those that do not release the bus, and those that release the bus when there is no need to use it even in the middle of a command, and then acquire the right to use the bus again when it becomes necessary to use the bus.

Conventionally, in each of these bus systems, communication between devices (
When transmitting/receiving data), it is necessary to specify a device number assigned to each device in order to identify the other device. Also, the sending device is a unique device! It is necessary to send the r number to indicate from which device the data on the bus came.

For this reason, conventionally, a line for transmitting the sending (fl, lI device number, and receiving side device number) is required, and a circuit for identifying the device number is also required for each device. All devices on the bus are equal as communication targets, and communication is possible between any devices, but on the other hand, data may be transferred to the own device at any time. The device design becomes extremely complicated, causing timing delays and increased hardware.As mentioned above, the conventional bus method has the advantage of being able to communicate between any devices On the other hand, it requires a line for transmitting the transmitting device number and the destination device number, and also has the disadvantage of requiring a device identification circuit for each device.Furthermore, each device has the disadvantage that it requires a line to transmit the transmitting device number and the destination device number. Because it is not possible to know in advance when the signal will arrive, this leads to loss of timing in the receiving circuit and an increase in the amount of hardware required.

[Purpose of the invention]

The present invention has been developed in view of the above circumstances, and eliminates the need for lines for transmitting device numbers on the sending side and receiving side, as well as identification circuits for device numbers, and furthermore, it allows data to be transferred to each device in advance. The purpose of the present invention is to provide a communication method between devices connected to a bus that can significantly simplify the system configuration and has a bus structure that can notify devices connected to the bus.

[Summary of the invention]

The present invention provides a bus-based information processing system in which a plurality of processing devices and a bus control device that determines the right to use the bus for each of these processing devices are connected on one bus. A signal line for each device individually notifies devices of bus use requests, a common signal line from the bus control device to each processing device to commonly notify data reception timing, and a signal on this signal line. As a bus structure, the bus structure has a signal line for each device to individually notify a specific processing device from the bus control device of permission to use the bus or the timing of fetching data on the bus. When transferring data between devices connected to
This makes it possible to efficiently transfer data between arbitrary devices connected on a bus without each device notifying or decoding the device number.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing an example of a system configuration for explaining an embodiment of the present invention. A system is shown in which a bus control device that determines the right to use the bus is also connected to the bus, and a main memory is connected to this bus control device. In Figure 1, 10 is a bus that connects each device in the system;
0... are, for example, input/output processing units (rop) connected to this bus 10, respectively.

A processing device (hereinafter simply referred to as a device) having a data transfer processing function such as a central processing unit (CPU), 30 a bus control device that determines the right to use the bus for each of these devices 20, 40 a main memory ( MEM).

FIG. 2 is a diagram showing an example of the connection configuration of the main signal lines of the bus 10 in the above configuration. In the figure, 1 to 14 are signal lines within the bus 10, 1 is a data/address line, and 12 is a bus request (BUS REQUEST) sent individually from the device 20 to the bus control device 30. 13 is a device-specific signal line for individually sending bus use permission (NEXT BUS USE) from the path control device 30 to the device 20 that has made a bus use request; 14 is a device-specific signal line 2 (J(i), 2 (
7(j) or a signal (TRANSMIT) that notifies the receiving device 20 of the timing of data reception in advance during data transfer from the path control device 30 to the device 20.
This is a common signal line that transmits. 31 determines the right to use the bus 10 in response to the bus usage request of each device 2Q inputted via the signal line 12, and grants bus usage permission to the corresponding device 2o via the signal line 13. When a data transfer command is issued between devices w20 (0, 20(j)), a bus right determining circuit 32 considers and decodes some data on the data/address line 11 as a device number, and decodes the data unique to the corresponding device. This is a data receiving device instruction circuit that instructs a corresponding device to receive data using the signal line 13 and common signal ffM14.

Here, Table 1 shows a specific example of the specifications of the bus 1o described above. In other words, the maximum number of connected devices 2o to be controlled by the bus control device tit30 is [1o] (+=1,
2,...10) is shown as an example.

Table 1 Here, each signal line shown in Table 1 above will be explained below.

CLOCK (abbreviation: IGcI, OCK) bus 10
This is the basic clock that determines the timing of In synchronization with this clock, each device contends for the bus, transfers data, etc.

See Figure 3.

Signals related to bus competition The priority of the bus is determined by the bus control device 30.

(1) BUS REQUEST (abbreviation ZBSIRQ)
i=0 to 9) This is a bus use request signal, and a unit device that wants to use the bus sets this signal to 1# at the beginning of a bus cycle.

Each device may continue to output this signal until it obtains the right to use the bus, but if it obtains the bus, it will stop outputting in the next cycle.

When writing to the interconnect cell in the bus control device 3θ, if the ZSTKFL signal is “1”, do not participate in bus contention until it becomes 0#.

(2) NEXT BUS USE (abbreviation; zBSi
OKl=0-9) The meaning of this signal differs depending on the state of the ZXMIT signal.

When ZXMIT is 110#, this signal is a signal indicating whether or not the device receiving this signal can use the bus in the next cycle.

The device that outputs the bus request (ZBSIRQ) samples this signal at the end of the bus cycle, and if it is '1'', it means that a unit with higher priority in terms of bus contention is not requesting the bus. , determines that it has acquired the bus, and uses the bus in the next bus cycle.

When ZXMIT is 0'1'', this signal is a signal indicating whether the unit receiving it receives data on the bus in that cycle.

(3) HOLD (abbreviation: ZHOLD) This signal is used when the unit that obtained the bus wants to continue using the bus in the next bus cycle.

When this signal is 1'', bus contention is stopped.

If the device wants to use the bus continuously for two or more cycles, after acquiring the bus, output KHOLD at the same time as the first data output.
1” and HOLD one cycle before the bus becomes unnecessary.
to o”.

The unit that outputs HOLD can use the bus unconditionally in the next bus cycle as well.

That is, HOLD functions as a bus request with the highest priority.

(4) IC5TACK FULL (abbreviation: ZST
KFL) This is a signal output from the bus control device feso, and the bus control device 3o is a signal output from the WRITE I from other devices.
NT-El: Indicates that the RRUPT CELL command cannot be accepted.

When attempting to write to an interwoven cell, each device checks this signal and, if it is 1m, postpones the bus request.

If a bus request has already been output in the cycle in which this signal becomes °'1#, writing to the intersect cell will not be performed even if the bus is acquired. After this signal becomes 0'', the bus request is accepted again, and after obtaining the bus, the data is written to the interlat cell (see FIG. 4(, )).

Before the ZSTKFL becomes 1", the device that has acquired the lotus writes to the intersect cell without any lag in the ZSTKFL, so the bus control device 30
Even during L output, it is possible to accept at least one access request (see FIG. 4(b)).

At least eight stacks are prepared.

Signals related to data/address transfer (1) ADDRESS/DATA (abbreviation: ZDA)
Dn n=00-31) 32-bit bidirectional line for transferring address or data.

In the case of memory access, the memory address is sent in the first bus cycle, and the data is sent in the next cycle.

7 Treasure is 32 bits, and can be a logical address or a real address. These are specified by the ZVMODE signal.

(2) ADDRESS/DATA PARITY (abbreviation: zDADPnn=0 to 3) The parity of the ADDRESS/DATA signal.

ADDRES S /DATA signals 8 signals with parity for every 8 trees.

The parity is an odd nokriti.

zDADOO~07's mother f4 ・-ZDADPO2
Parity 4-ZDADP IZDAD of DAD08-15
16-23 (DA Lite 4-ZDADP2ZDAD 24
~31 (D t4sf i=・ZDADP3(3)
COMMAND/ZONK (abbreviation; zCOMznn=
0 to 3) This signal is used for bus commands and zone designation of write data.

(~ CO Tomo AND This signal is normally used as a command.

Command codes and meanings are shown in Table 2.

Table-2 The function of each command is shown below.

(a) NOP No action is taken on the device.

However, please reply CONFIRM (see below) normally.

This command is used to check the operation of the bus and devices.

(b) ADDRESS TRANSLATE Requests address translation to the bus control device 30. The bus control device 30 converts the logical address into a real address in the same way as a normal memory access command, but instead of accessing the memory, it returns the converted real address. 2(c)
RESPONSE DATA Indicates that response data to a previously output read command is being output from the bus controller to the bus.

(d) READ INTERRUPT CF, LLC
PU is the IC (INTERRUPT) of the spring control device 30.
CELL) is used when reading. If the VCIC stack becomes empty after executing this command, the path control device 30 stops the interrupt signal to the CPU.0(e) 5TART
Ilo (abbreviation SIO command) I10 Uni, ) (
Operation instructions for IOP, DISC/MT C0NTR0LLER, etc.). This command ends in 3 bus cycles. In the first cycle, the CPU sends the unit number along with this command via the ZDAD line. The path control device 30 decodes the sent unit number and issues ZBSiOK and ZXMIT in the next cycle. In the third cycle, the CPU sends the CPH address along with this command via the ZDAD line. ZB in previous cycle
The unit designated by SiOK receives the command and CPH address in this cycle. If this unit is in the BUSY state, it will send a message to that effect on the CONFIRM line, and the CPU that issued the S■0 command will receive this. This command is also used for communication between CPUs when using multiple CPUs.

(f) WRITE INTERRUPT CELLI
Used to send interrupt data from lo to BCU.

Interrupt data (INTERRUPT CELL) is sent on the address/data line along with this command. I
NTERRUPT CELL consists of two words and is sent on the bus twice in succession. The ICs sent to the path control device 30 are stacked, and an interrupt is issued from the path control device 30 to the CPU.

When executing this command, it is necessary to check ZSTKFL.

(g) READBCU-REGISTER Reads various registers in the path control device 30. Register designation is based on a register designation code on the ZDAD line that is sent at the same time.

(h) MEMORY READ 5INGLE Used to read one word of data from memory. Outputs the memory address on the bus along with this command.

When the memory receives this command, it reads one word of data from the specified address and sends RESPONE DA.
It is sent back to the transmitting device along with the TA command.

(i) MEMORY READ DOUBLE Used to read 2 words of data from memory. Outputs the memory address on the bus along with this command.

When the memory receives this command, it reads 2 words of data from the specified address and sends RESPONE DA.
It is sent back to the transmitting unit in two pass cycles together with the TA command.

The data returned first is the word specified by the memory address.

(j) MEMORY READ QUADRUPLE
Read 4 words of data from memory. Bus control system @
When the SO receives this command, it reads four words from the memory, divides this data into four cycles, and sends it back. Bits 28 to 31 of the specified address are assumed to be zero, and data is transferred from the beginning of the 4-word boundary.

(k) WRITE BCU-REGISTER Writes data to various registers in the path control device 30. This command consists of two bus cycles; the first cycle sends a code specifying the register, and the next cycle sends the write command tf-.

(1) MEMORY'rEST & SET 1 from memory
Reads the word data and writes all ``1'' (FFFFFFFFFF) to the read address. Sequence u MEMORY READSINGLE on the path
It is similar to

(m) MEMORY WRITE BY ZONE
5INGLE Used to write one word of data to memory. This command consists of two consecutive bus cycles; in the first cycle, a memory address is output on the path together with this command, and in the second cycle, write data and ZONE (described later) are output.

(n) MEMORY WRITE BY ZONE
Used to write 2 words of data to DOUBLE memory. This command consists of three consecutive bus cycles; in the first cycle, a memory address is output on the path along with this command, and in the second and third cycles, write data and ZONE are output.

The data sent first is the word specified by the memory address.

(B) Z ON E During the data transfer cycle following the memory write command, Z
COMZn is used as a write byte zone designation (ZONE).

The 4 bits of Z ONE indicate which position of the 4-byte wide data is to be written to memory.j5, ZONE
Only the data in the byte position where 1" is set is rewritten. An example of this zone designation is shown in Table 3. The ** section indicates the byte position to be rewritten.

Table-3 (4) COMMAND/ZONE PARITY (
Abbreviation: ZCOMZP) Parity for the COMMAND/ZONE signal.

The parity is set to odd number nine.

(5) REQUEST FROM CPU/IO (abbreviation: ZCPUIO) A request to the path control device 30 is
From U (ZCPUIO=”i’) or I/o
<ZCPUIO="0"). This signal determines which bit will be used as the present bit of the PTW during address conversion. Since this line is resolved up and normally becomes "0", the I10 unit does not need to output this signal.

(6) REAL/VIRTUAL, MODE (abbreviation: ZVMODE) Specifies whether the address sent to the bus control device 30 is a real address or a virtual address in the cycle in which the address is sent on the bus.

(7) END OF CYCLE (abbreviation: ZEN
Di) When the bus control device 30 is accessed, DAC is returned together with ZENDi from the second cycle onward.

(8) BCU ACTION C0DE (abbreviation:
ZBACn n=0 to 3) Returns the operation of the path control device 30 as a 4-bit code.

Code 00XX Normal 01 X
NEA1001 Undefi when in REAL MODE
ned REG-CODEL 010 IC5TACK
EMPTYllXX Memory Double-
Error (9) FIR8T COMMAND (abbreviation: ZFSTCM) When the command sequence spans multiple cycles, the first cycle, or in the case of a command that ends in one cycle, it becomes 1” in that cycle and the first command is sent. represents.

(11TRANSMIT (abbreviation; ZXMIT >Z
This indicates that data will be sent from the path control frame N'30 to the unit whose BSiOK is 1" in the next cycle. However, ZXMIT is used in a special way in the SIO command.

Transfer confirmation signal (1) CONFIRM (abbreviation: ZCONFi n=
o~3) A signal for confirming reception, which is sent onto the path two bus cycles after address/data reception.

The transmitter checks the C0NF I RM line in the second bus cycle to confirm normal operation.

C0NF I RM meaning and code 1100"...NORMAL data, commands, addresses, etc. Indicates that the message was received correctly.

°101”・・・BUSY The receiving device is performing other processing. data, commands, addresses Indicates that you cannot receive the same.

*A unit that has issued a read request to the memory for l10f times must not return BUSY in response (RESPONSEDATA).

"10"...BUS PARITY ERRORZD
Indicates that there was a /'P property error on the AD line or Z COMZ line.

°°11”...No RESPONSE/Access to non-existent Units+, ILLEGAL BUS 5EQUENSE, IL
LEGAL COMMAND, if there is no response due to unit abnormality, etc., the result will be No RESPONSE.

Interrupt-related signal INTERRUPT REQUEST (abbreviation: ZI
NTRQ, ) Activation of Ilo and interrupt from Ilo are performed in the following order.

(a) CPU1d sends the CPH address to the unit specified by the SIO command. (Transmission and reception of SIO) (b) The unit that receives the SIO starts I10 processing.

(C) After the processing is completed, each unit transfers to the bus control device 30. 2. Write the intertalk cell to the IC stack of the bus controller 30 using the command. However, IC5tack Full
In that case, do not issue the Write Interrupt Ce1l command.

(d) The bus control device 30 issues an interrupt to the CPU when an entry is made to the stack. (Use ZINTREQ) (e) When the CPU receives an interrupt signal, it
0 to request cell data.

(f) After transmitting data, the bus control device 30 continues to output ZINTRER until the IC stack becomes empty, and stops ZINTREQ when it becomes empty.

(g) When there is only one free space left in the IC stack of the bus control device 30, the bus control device 30 uses ZS TK.
Prohibit cell data from being sent using FL.

Other signals TIMERINTERRUPT (abbreviation; ZWDIN
T) wDT (Watcb dog) of the bus control device 30
When an interrupt condition (timer) occurs, this line is used to notify the CPU.

Figures 5(a) and 5(b) respectively illustrate data communication operations between devices in an embodiment of the present invention.
) shows the sequence of the read command from the main memory 40, and FIG. 10(b) shows the sequence of the input/output start command.

An embodiment of the present invention will now be described with reference to FIGS. 1 to 5(a) and (b). First, taking as an example the sequence of the main memory read command (memory read command) shown in FIG.
The operation of data communication control between 0 and 0 will be explained. A plurality of devices 20 connected on the bus 10...
When a ZBSiRQ (bus use request) is sent from the device 20(i), this signal is accepted by the bus right determining circuit 3 in the bus control device 30 via the signal line 12. In response to the request, the bus use right determining circuit 31 in the bus control device 30 determines the bus use priority, and when the bus use is permitted, the corresponding device 20(i) 1, sends ZBSiOK (bus use permission). Device 20 (i) Dove (7) Z
When receiving BSiOK, it recognizes that bus 10 (D can be used) and uses bus 10 in the next bus cycle. In other words, here, the command (memory read command)
, address, and ZFSTCM are sent to the bus controller 30 via the bus 10. The main memory 40 is read and controlled according to the information on the bus 10. At this time, in the bus control device 30, the command, address, etc. on the bus 10,
The bus right determining circuit 31 has already recognized from which device ZFSTCM and ZFSTCM were sent. When the bus control bag jfl 30 sends data read from the main memory 40 to the device 20 (i), the bus control bag jfl 30 sends the data read from the main memory 40 to the device 20 (i) via the bus right determining circuit 31 and the signal line 13.
ZBSiOK is sent to the signal line 7.9(i) specific to 1), and ZXMIT is sent to the common signal line 14 in the same cycle. The device 20(1) receives the signal line 13Y9ZBSiOK and sends the signal m14 to pZ
When receiving XMIT, it recognizes the data reception timing and receives the command and data (read data) in the next bus cycle.

Next, the input/output start command (SIO
Taking the sequence of command) as an example, device 2' (1)
The operation of data communication control during #2' (J) will be explained. Here, the processing device on the sending side is C
PU 2 (J(i), and the processing device on the receiving side is IOP
20 (j). CPU 20 (
The operation until i) obtains permission to use the bus 10 is the same as in the case of the memory read command described above.

When the CPU 20(i) is permitted to use the bus 10, that is, upon receiving ZBSiOK via the signal line 13, the CPU 20(i) issues a command (SIO command) in the first bus cycle.
. When the bus control device 30 receives the information on the bus 10, it interprets the command and determines that it is a command for communication between devices, that is, an input/output start instruction command (SIO command) in this case. After decoding the device number (DID) on the data/address line 11 and recognizing the other device (IOP20 (j)), in the next bus cycle, the device number (DID) on the data/address line 11 is decoded. o (
It sends ZBSiOK to the threat line 1.9 (j) specific to j), and at the same time sends ZXMIT to the common signal line 14. IOP,? o (j) is the signal line 73 (j
), and at the same time receives ZXMIT via the signal line 14, it recognizes the data reception time,
Commands and data on bus 10 are received on the next bus cycle. Here, the CPU 20 (i) issues an input/output start instruction command (sr).

command) and the start address of the channel command are sent onto the bus 1θ, and this is the IOP, ? o (j). In this way, CPU 20(i) to rop,? Command/data transfer to o(j) takes place.

As described above, the devices 20... and the bus control device 30 (
between the main memory 40) and the device 20(I).

20(j) is optionally performed via bus 10. With such a bus control means, it is only necessary to control transmission and reception so that each device on the bus 10 can always communicate only with the main memory 40 via the bus control device center 30, and communication between devices can be controlled. There is no need to consider the control for

Therefore, transmission lines for transmitting device numbers, receiving device numbers, recognition circuits for device numbers, etc. are not required, and the system configuration can be greatly simplified. Also, when self-installed JFK data is sent, it is always notified in advance, so timing design becomes easy and the hardware configuration can be simplified in this respect as well.

〔Effect of the invention〕

As detailed above, according to the present invention, in a bus type information processing system in which a plurality of processing devices and a bus control device that determines the right to use the bus for each of these processing devices are connected on one bus, , a signal line for each device that individually notifies the bus use request from the processing device to the bus control device, and a common signal line that commonly informs the data reception timing from the bus control device to each of the processing devices. In combination with the signal on this signal line, the path control device has a device-specific signal line that notifies a specific processing device of the permission to use the bus or the timing of fetching data on the bus. By adopting a bus structure consisting of It is possible to provide a communication method between devices connected on a bus that can efficiently transfer data between the devices.

[Brief explanation of drawings]

3 and 4 (a) and 4 (b) are diagrams for explaining the timing of bus use in the above embodiment, respectively.
FIGS. 5(a) and 5(b) are diagrams each showing an example of a bus command sequence for explaining the operation of the above embodiment. 10...Bus, 11...Data/address line,
12.13... Signal line for each device, 14... Common signal line, 20... Device (processing device), 30... Bus control device, 3... Bus usage right determining circuit, 32. . . . Data receiving device instruction circuit, 40 . . . Main memory. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 3 Sub 2 l 11 Figure 4

Claims (1)

[Claims] In a bus-type information processing system in which a plurality of processing devices and a bus control device that determines the right to use the bus for each of these processing devices are connected on one bus, each of the processing devices individually controls the bus control device. a first device-specific signal line for sending a signal to the device; a means for sending a bus use request via the first device-specific signal line; and a device for individually sending signals from the bus control device to each of the processing devices; a second device θ separate signal line;
means for transmitting a bus use permission to the processing device that requested the bus use in response to the bus use request via the second device-specific signal line; a common signal line for sending a signal, a means for sending a reception timing notification signal to notify the timing of data reception when transferring data to the processing device via the common signal line; means for decoding part or all of the data on the data line as a device number during data transfer between devices, and recognizing the corresponding device; and means for generating the second device-specific signal based on the recognized device number. and a means for sending a signal instructing data reception to the processing device indicated by the device number via the common signal line, and receiving data during data transfer between devices connected on the same bus. A communication system between devices connected on a bus, characterized in that the bus control device recognizes and gives instructions to the side devices.