JPS60163761U - charge coupled device - Google Patents
charge coupled deviceInfo
- Publication number
- JPS60163761U JPS60163761U JP1984049965U JP4996584U JPS60163761U JP S60163761 U JPS60163761 U JP S60163761U JP 1984049965 U JP1984049965 U JP 1984049965U JP 4996584 U JP4996584 U JP 4996584U JP S60163761 U JPS60163761 U JP S60163761U
- Authority
- JP
- Japan
- Prior art keywords
- type semiconductor
- conductive type
- well region
- wiring
- coupled device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Networks Using Active Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は背景技術の問題点を説明するための１つのＣＣ
Ｄを示す断面図、第２図Ａ、Ｂは同じく背景技術の問題
点を説明するための別のＣＣＤを示すもので、Ａは平面
図、ＢはＡのＢ−Ｂ線に示す断面図、第３図は本考案Ｃ
ＣＤの実施の一例を。
′ 示す断面図、第４図は本考案ＣＣＤの別の実施例
を示す断面図、第５図Ａ−Ｃは出力信号用配線に寄生す
る実効的容量を小さくしたＣＣＤの出力部の一例を示す
もので、同図Ａは回路図、Ｂは平面図、Ｃは同図ＢのＣ
−Ｃ線に沿う断面図、第６図は出力ゲート電極及びプリ
チャージゲート電極と、フローティングディフュージョ
ン領域との間の実効的容量を小さくしたＣＣＤの出力部
を示す断面図、第７図Ａ、 Ｂは増幅器の実効的入力容
量を小さくしたＣＣＤの出力部の各別の例を示す断面図
、第８図Ａ、 Ｂはゲインをきわめて１に近い値にでき
る増幅器を示すもので、Ａはその構造を示す断面図、Ｂ
は回路図、第９図Ａ、 Ｂは寄生バーイポーラトランジ
スタがオンしにくくなるようにした増幅器の各別の回路
例を示す回路図、第１０図及び第１１図はグランド電極
により出力回路を保護するようにしたＣＣＤの各別の例
を示すもので、その両図においてＡは断面図、ＢはＡの
Ｂ−Ｂ線に沿う断面図である。
符号の説明、１・・・第１導電型半導体基板、２・・・
第２導電型半導体ウェル、５・・・絶縁膜、７，７゜７
・・・転送りロックパルス用配線、９，９・・・直流電
圧印加用配線、１０・・・信号用配線。
第３図 ９ ９ １０
ノ ノー ノ
ー８７７７５５
１」−，１＋１嘗゛
−１
ｉｎ
１
Ｍｐ Ｍｄ
ｌ
ＭＩ Ｍｄ 。Figure 1 shows one CC for explaining the problems of the background technology.
A sectional view showing D, FIGS. 2A and 2B show another CCD for explaining the problems of the background art, A is a plan view, B is a sectional view taken along the line B-B of A, Figure 3 shows the present invention C.
An example of CD implementation. 4 is a sectional view showing another embodiment of the CCD of the present invention, and FIGS. 5A to 5C show an example of the output section of the CCD in which the effective capacitance parasitic to the output signal wiring is reduced. Figure A is a circuit diagram, B is a plan view, and C is a diagram of Figure B.
6 is a sectional view showing the output part of the CCD with a reduced effective capacitance between the output gate electrode, the precharge gate electrode, and the floating diffusion region; FIGS. 7A and B 8A and 8B are cross-sectional views showing different examples of the output section of a CCD in which the effective input capacitance of the amplifier is reduced, and FIGS. 8A and 8B show an amplifier that can make the gain extremely close to 1. Cross-sectional view showing B
is a circuit diagram, Figures 9A and B are circuit diagrams showing different circuit examples of an amplifier that makes it difficult for parasitic bipolar transistors to turn on, and Figures 10 and 11 are circuit diagrams in which the output circuit is protected by a ground electrode. In both figures, A is a cross-sectional view, and B is a cross-sectional view of A taken along line B--B. Explanation of symbols: 1... first conductivity type semiconductor substrate, 2...
Second conductivity type semiconductor well, 5...insulating film, 7, 7°7
... Wiring for transfer lock pulse, 9,9... Wiring for applying DC voltage, 10... Wiring for signal. FIG. 3 9 9 10 NO NO NO 877755 1''-,1+1嘂゛-1 in 1 Mp Md l MI Md.
Claims (1)
導体ウェル領域が形成され、半導体表面上に絶縁膜を介
して形成される転送りロックパルス州名配線が前記第２
導電型半導体ウェル領域の上方に位置され、半導体表面
上に絶縁膜を介して形成される直流電圧印加用配線及び
信号用配線が半導体基板の上記第２導電型半導体ウェル
領域の形成されていない部分の上方に位置されてなるこ
とを特徴とする電荷結合素子。A second conductive type semiconductor well region is selectively formed on the surface of the first conductive type semiconductor substrate, and a transfer lock pulse state wiring formed on the semiconductor surface via an insulating film is connected to the second conductive type semiconductor well region.
Direct current voltage application wiring and signal wiring located above the conductive type semiconductor well region and formed on the semiconductor surface via an insulating film are located in a portion of the semiconductor substrate where the second conductive type semiconductor well region is not formed. A charge-coupled device characterized in that it is located above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984049965U JPS60163761U (en) | 1984-04-05 | 1984-04-05 | charge coupled device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984049965U JPS60163761U (en) | 1984-04-05 | 1984-04-05 | charge coupled device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60163761U true JPS60163761U (en) | 1985-10-30 |
| JPH0445240Y2 JPH0445240Y2 (en) | 1992-10-23 |
Family
ID=30567643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984049965U Granted JPS60163761U (en) | 1984-04-05 | 1984-04-05 | charge coupled device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60163761U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58125872A (en) * | 1982-01-21 | 1983-07-27 | Nec Corp | charge coupled device |
-
1984
- 1984-04-05 JP JP1984049965U patent/JPS60163761U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58125872A (en) * | 1982-01-21 | 1983-07-27 | Nec Corp | charge coupled device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0445240Y2 (en) | 1992-10-23 |
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