JPS60164355A - Manufacturing method of photodetector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a light receiving element in which a photodiode and a field effect transistor are integrated on the same semiconductor substrate.

(Prior art) In recent years, PIN photodiodes and field effect transistors (
A light-receiving element called PIN-FET using a PIN-FET (hereinafter abbreviated as T) is attracting attention as a light-receiving element with excellent performance similar to an avalanche photodiode.

As PIN-FET, PIN photodiode and G
A device using a A s -F ET is currently available for commercial use, but the aim is to further miniaturize the device and reduce stray capacitance to one region for high-speed response. A structure was created in which both were integrated on the same semiconductor substrate.
are doing.

For example, Ohnaka et al. “InGaAs monolithic PIN-P
"D/JPET photodetector" (IEICE technical research report 0
QE83-70, pages 47-54), InGaAs fgi was grown on a semi-insulating InP substrate, and PI
An fcPIN-FET formed by integrating an N photodiode and a junction type PET has been announced.

FIG. 1 is a sectional view of an example of a conventional PIN-FET.

This PIN-FET is
'ET' is shown. In FIG.

111 is a semi-insulating InP substrate, 12 is this InP substrate 1
1 formed by liquid phase epitaxy on n*I n o
, 5a Ga O, 47 AsI@, 13 is A u /
S n / A u layer, 14 is A u N b15! I
'i Polyimide layer for passivation, 161°16
2 and 17 are Zn diffusion regions. Diffusion consists of deep diffusion reaching the semi-insulating InP substrate 11 to reduce the junction capacitance of the bonding pad portion of the gate, and shallow diffusion to form the gate and light receiving portion. is created, and the diffusion region 1 is also created by shallow diffusion.
61 and 162 are made. Diffusion area 162 is PIN
The P-side region of the photodiode and the diffusion region 161
becomes the gate region of the contact type FET.

In order to increase the reception sensitivity of PIN-FET, junction type FE
It is desirable that the mutual conductance of T is large, and the carrier concentration of the layer 12 is n = 5
About m-3 is preferable. - It is desirable that the junction capacitance t of the PIN photodiode is small, and for that purpose, the carrier concentration is preferably as low as 1. Using the vapor phase growth method, it is possible to increase the carrier concentration to about `` `` '' × 1015 (Ml 3). Therefore, in the structure shown in the bit diagram, the contact @ff1 FET and the PiN photodiode are The drawback is that it is rarely possible to simultaneously achieve optimum carrier concentrations for both cases.

(Object of the invention) The object of the invention is to eliminate the above-mentioned drawbacks and to develop a junction FET and i
' i N 7 Otodiode is turned off and independent vcH
An object of the present invention is to provide a light-receiving element with an integrated structure that enables appropriate design.

(Structure of the Invention) The uninvented light receiving element includes a semi-insulating semiconductor substrate, a first semiconductor layer of one conductivity type provided on a part of the semiconductor substrate and having a carrier concentration of nml, and the 410 semiconductor a second semiconductor layer of one conductivity type provided on the layer and on the semiconductor substrate, the second semiconductor layer having a carrier concentration of 1, the first carrier concentration being 1; From the semiconductor layer of @
A photodiode formed of the first semiconductor and opposite conductivity type regions provided to reach into the first semiconductor layer, and an opposite conductivity type region provided in the second semiconductor layer. A contact type field effect transistor having a conductivity type region as a gate, and a contact type field effect transistor provided on the surface of the second semiconductor 1 and on both sides of the gate and having nt poles as a sheath and a drain. .

(Example〕 Next, an example of a single light beam will be described with reference to the drawings.

FIGS. 2(a) to 2(C) are cross-sectional views shown in the order of steps for explaining a manufacturing method of an embodiment U of the present invention.

First, as shown in FIG. 2(a), a semi-insulating InP substrate 211r is etched to form a step portion of about 3 μIn. Next, a first semiconductor layer containing a first carrier concentration n1 on the entire surface is formed of Si, etc.tn1-IXIO15cn.
N-type I n O,53Gaαa containing about 4-3
7AS In 22 is grown to a thickness of about 3 μm by vapor phase growth.

Next, as shown in FIG. 2(b), the I"0.53GaO, 47As layer 22 grown on the surface of the high step portion is removed by etching to make the surface almost flat. At this time,
A figure 7 groove is created as shown, but it is preferred that this groove be as small as possible. Next, the carrier concentration n1 of Ml
Higher second carrier concentration nz (nz > nx
) as the second semiconductor layer with n'''
=” N-type I n containing approximately ×1015cm-3
A 0.53QaO,47As layer 23 is grown to a thickness of about 1 μm by vapor phase growth.

Next, as shown in FIG. 2(C), after a P-type impurity such as Zn is diffused to form six deep P-type diffusion regions 24 that reach the InP substrate 21, the same P-type shallow diffusion regions 24 are formed. 251,
252 is formed. The depth of the diffusion regions 251° and 252 is set to rL O, 5ttm, 1.2, can.

Next > Au/Sn/Au layer 26. An electrode is formed using the Au layer 27, and a polyimide layer 28 for packvation is applied.

PM diffusion region 252, 53 Ga
g, and the 47 As layer 22 constitute the light receiving part of the photodiode.

The deep diffusion region 24 becomes the bonding part.

Furthermore, the P-type diffusion region 251 serves as a gate, and two nIC layers 26 are formed on both sides of the gate.
．． A junction FET is formed in which the Au layer 27 serves as a sheath and a drain (Yumei's effect).As described above in detail, according to the present invention.

The carrier concentration of the active layer of the junction FET and the light absorption layer of the photodiode can be independently designed.

The gate length and gate width of the junction FET are each 5 μm.
and 100 μm, the mutual conductance is 1
5m5 is obtained, which is as large as a GaAsFET. Also, the light receiving diameter of the photodiode is set to 80μ.
ml, the junction capacitance of the shifted diode can be as small as 0.29F by applying a reverse voltage of 5μ.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an example of a conventional PIN-FET, and FIGS. 2(a) to 2(C) are sectional views showing the order of steps for explaining a manufacturing method of an embodiment of the invention. 11... Semi-insulating 1nP substrate, 12...
...In□, 53Ga g, 47 As layer, 13...
...Au/Sn/Au layer, 14Aul@, 15...
... Polyimide layer, 17 ... PM diffusion region, 21 ... Semi-insulating InP substrate, 22.
...In 0.53GaO,47As layer (i
f semiconductor 1ull), 23...Ing, 53
Ga (1,47As layer (second semiconductor layer), 24...
...pi diffusion region, 26-...Au/Sn/Au
Ji! , 27...AnlLzs...
Polyimide layer, 161. 162...P-type diffusion region, 251,252...P-type diffusion region.

Claims (1)

[Claims] a semi-insulating semiconductor substrate; a semiconductor layer of one conductivity type if having a carrier concentration of n1L1 provided on a portion of the semiconductor substrate; a second semiconductor layer of one conductivity type having a second carrier concentration higher than that of the first carrier 811; A photodiode is formed of a region of opposite conductivity type provided in the second semiconductor layer and the first semiconductor layer, and a region of opposite conductivity type provided in the second semiconductor layer is used as a gate, and A junction field effect transistor whose source and drain are tL7C electrodes provided on the surface of the semiconductor layer and on both sides of the gate.