JPS601654B2 - Information processing system integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit in which an information processing system such as an electronic computer or an electronic exchange is integrated into one chip.

With the rapid development of semiconductor technology, the scale of integration on a single chip is increasing year by year.

At present, random access memories (hereinafter referred to as RAM) or 16-bit microcomputers have been realized with one chip and one K bits. Therefore, in the near future, the entire information processing system consisting of main memory, central processing unit (hereinafter referred to as CPU), etc., excluding input/output devices, disk devices, etc., will generally be called the main body system on one chip. It is highly anticipated that this will be realized. Hereinafter, such a main memory, CPU, etc. integrated into one chip will be referred to as an information processing system integrated circuit (sometimes abbreviated as system LSI in the following explanation). If we were to test such system LSIs (including tests at the manufacturing stage) using conventional methods, we would test each functional block such as the main memory or CPU, or
Alternatively, the entire combination thereof, that is, the information processing system, is tested, but in either case, the test is performed by connecting to a tester.

In general, when testing BI whose functions have become more complex and its scale has increased outside of testing, it takes an enormous amount of time, and there is a drawback that the testing cost accounts for a large proportion of the overall cost. In a system LSI, it becomes even larger. In addition, such system LS
In order to manufacture I with high yield, it is also possible to install more than the required number of CPUs or main memories on the same chip to make them redundant, and to connect the normal ones to form one information processing system. However, in this case, each C
Testing of the PU and main memory is required, thus exacerbating the aforementioned drawbacks. It is an object of the present invention to eliminate the above-mentioned drawbacks, and to
L that realizes an information processing system consisting of U on one chip
In SI, by providing means for testing each function of the information processing system on the chip, tests can be executed independently within one chip without using a separate tester (hereinafter referred to as self-testing). ), and furthermore, to provide an information processing system integrated circuit which makes it possible to install more than the required number of CPUs and main memories in the information processing system and to appropriately connect the normal CPUs and the normal main memories. .

In order to achieve such an object, the present invention provides an information processing system comprising a main memory that stores programs and data, and a central processing unit that performs various calculations and controls based on the contents of the main memory; a persistent memory containing instructions for testing the health of the system;
The information processing system, the fixed memory, and the test auxiliary means are integrated on one chip, and includes test auxiliary means for executing the test according to a test mode specified from the outside and outputting the test results to the outside. configured,
A connection circuit that connects the central processing unit and the main memory as appropriate by installing more than the required number of the central processing unit and the main memory, and a rewritable non-volatile memory that controls the connection state of the connection circuit. The present invention is characterized in that it is provided with a connection information holding circuit made of a magnetic element, and a connection information changing means for changing the contents of the connection information holding circuit according to the test result. The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which an information processing system is configured with one CPUI and one main memory 2, and a procedure for testing the normality of this information processing system. Fixed memory that recorded
A system LSI 5 is constructed into one chip by adding a test auxiliary section 4 (referred to as OM) 3 and a test assisting section 4 that assists in test execution.

The system LSI 5 has terminals for data signals and control signals used in general information processing systems (not shown in FIG. 1), as well as a test mode designation signal 6 and a test result display signal for causing the system LSI 5 to execute a self test. 7
It is equipped with a terminal 7 for receiving. In this example, since the test means is built into one chip as shown in FIG. ) is added, Test-ROM3
The CPU and the main memory 2, that is, the information processing system, are tested according to a test procedure (hereinafter referred to as a test program) stored in the test program, and the results are outputted as a test result display signal 7. On the other hand, when logic level "0" is applied as the test mode designation signal 6, it is theoretically possible to operate the system as a general information processing system consisting of the CPUI and the main memory 2. Hereinafter, a specific example of the configuration of the test auxiliary unit 4 and an example of the test method will be shown.
It will be shown that self-testing is possible in the case of the configuration shown in FIG.

Note that there is a possibility that this self-test may not be performed without error, but this will be discussed later. FIG. 2 shows a specific example of the configuration of the test auxiliary section 4 in FIG.
This is shown in relation to the entire SI5. As shown in the figure, the test auxiliary unit 4 includes an oscillator 1 that generates a clock signal that defines the operation timing of the CPU during a self-test.
1. A time window signal 12 indicating the time when the test ends normally, and a time over signal 13 for prohibiting the clock signal from the oscillator 11 thereafter.
a timer 14 that generates a logical product, AND gates 15 to 18 that take appropriate ANDs, a delay line 19 with a delay time 6, a flag 20 that stores whether the test result is correct and outputs a test result display signal 7 to the outside, Then, the timer 14 is reset and a program counter (not shown) in the CPU is initialized to indicate the start address of the test program (the initial set terminal 27 of the CPU, which will be described later, is connected to the program counter therein). It is composed of a time constant circuit 21 consisting of a power supply V of voltage V, a resistor R, and a capacitor C. Here, the circles shown for the CPU 1, timer 4, and AND gates 15 and 16 indicate signal inversion inputs. Note that the timer 14 is incremented by the output of the AND gate 15, and is reset by a positive pulse applied to the reset terminal 14R. CPUI is clock input terminal 2
2, and a normal clock 24 from the outside is normally supplied to this input terminal 22 via an OR gate 23.
During self-test, AND gate 1 of test auxiliary circuit 4
5 to provide a self-test clock 25 from C
The PUI operates based on either of these clocks.

Furthermore, the CPU has a test designation terminal 26 in addition to input/output terminals for general calculations and control, and the above-mentioned test mode designation signal 6 is applied to this terminal 26, thereby determining whether or not a self-test is in progress. . Further, in order to initialize the CPU program counter, the initial set terminal 27 connected to the connection point a between the resistor R and the capacitor C and the test result information are sent to the AND gates 16 and 1 of the test auxiliary section 4.
It has a test result terminal 28 for sending out to 7. Oscillator 11
output, test mode signal 6 and time over signal 1
3 to the AND gate 15, and this AND gate 15
Take out the self-test clock 25.

This self-test clock 25 is added to the timer 14.
A time window signal 12 obtained from timer 14 is supplied to AND gates 16 and 17. Test result information is also added to these AND gates 16 and 17. The output of the AND gate 16 is connected to the AND gate 18 through the delay line 19, and the output of the AND gate 17 is connected directly to the AND gate 18.
and its AND output is applied to the set input terminal of flag 20. FIG. 3 shows the addressing of Test-ROM 3 and main memory 2, with addresses 0 to An-
, is the main memory area, and addresses An to AI are Te.
This is the st-ROM area.

In other words, the starting address of the test program stored in the Test-ROM 3 is An, and the address An is set in the program counter in the CPUI at the time of initial setting. FIG. 4 shows a flowchart of the test program according to the present invention. In the present invention, as shown in the figure, when all of the several tests are normal, the test result signal obtained from the above-mentioned terminal 28 is A test program is created so that the test program switches from "0" to "1" and immediately stops the test if there is an error in any test.

5A to 5N show time charts from the start of the self-test to the end of the test when the information processing system consisting of the CPU I and the main memory 2 are all normal, and each signal corresponds to that in FIG. 2.

The flow from the start to the end of the Komotozuki test shown in FIGS. 5A to 5N' will be explained below. First, power is applied to the system 1 as shown in FIG. 5A, and the oscillator 11 starts operating as shown in FIG. 5D.

By setting the time constant of the circuit consisting of the resistor R and capacitor C shown in FIG. 2 to be larger than the rise time of the power supply, the potential at point a gradually rises as shown in FIG. After the power is turned on, "1" is applied to the reset terminal 14R and the initial set terminal 27 of the CPUI for a short period of time until the voltage at point a exceeds the threshold voltage Vth of the inverting logic element of these terminals. (See Figure 5C). This makes it possible to reset the timer 14 and set the start address An of the test program in the program counter in the CPUI. Next, the test mode designation signal 6 is changed from "0" to "1" as shown in FIG. 5E. Here, the output of the oscillator 11 is applied to the clock input terminal 22 of the CPUI through the AND gate 15 and the OR gate 23 (see FIG. 5F), and the timer 14 starts counting the clock 25, starting the self-test. be done. Let us now assume that all system LSIs are normal.

In this case, the CPUI sequentially executes the tests and eventually changes the test result terminal 28 from "0" to "1". The time from the start of the test to the signal change, that is, the number of clocks, should be known in advance when creating the test program, so the time window signal 12 shown in Figure 5 should be generated to include this time. Configure timer 4. Therefore, as shown in FIG. 5, the test result information 28 changes from "0" to "1" in the middle of the time window signal 12, and is flagged by the AND gates 16, 17 and 18 and the delay line 19 shown in FIG. The input signal is created (see Figure 5 J, K, L and M), the flag 20 in Figure 2 is set, the test result display signal 7 changes from "0" to "1", and the test result is output to the outside. It is displayed that the result is normal, that is, the system LSI 5 is a good product. Next, as shown in FIG. 5G, the time over signal 13 becomes "1" with a slight delay from the time window signal 12, and the output of the AND gate 15 becomes "0".
Therefore, the self-test clock 25 to the CPUI is prohibited. Note that the above is a case where the system LSI 5 is normal, but if there is a defect in the CPUI or the main memory 2, the self-test will stop midway or the test program will run out of control.

In any case, in these cases, the test result will not change from "0" to "1" while the time window signal 12 is "1" (actually, the probability may be very close, so it is not perfect). Although this is not a self-test, it poses no problem in practical use), so the flag 2 is not set and the test result display signal 7 remains at "0". That is, in this case, it can be seen that the system LSI is a defective product. Then, the self-test clock 25 to the CPU 1 is inhibited by the time-over signal 13, and the CPU 1 is stopped. The above is based on the assumption that the Test-ROM 3 and the test auxiliary part 4 are normal, and these parts 3 and 4 must be tested in advance or by majority logic (for example, T
It is preferable to use a configuration in which errors can be masked by using a method such as M old). However, since the amount of these metals is small compared to the CPUI and main memory 2, even when testing, the CPU
This is easier than testing U1 and main memory 2. or,
The above self-test shows normal CPU and main memory 2.
Therefore, a defective product may be determined to be a good product. However, in this embodiment, a non-defective product is not determined to be a defective product. Therefore, although system LSIs that have passed the above-mentioned self-test may be required to undergo conventional tests using a conventional tester, the number of system LSIs to be retested using this tester is always smaller than the original number. . That is, in this case as well, the total test time is reduced (not including self-tests). Furthermore, when the non-defective rate of the system LSI is low, the effect of this self-test is even greater. Although the self-test procedure etc. have been explained above based on FIGS. 1 to 5, the present invention is not limited to the configuration shown in FIG. 2, and can naturally include other configurations and test procedures. The self-test of the present invention can be carried out by installing in the system 15 a Test-ROM 3 containing test procedures and a test auxiliary section 4 for executing, stopping, or controlling the self-test.

Next, another embodiment of the present invention is shown in FIG.

Here, a case is shown in which the system LSI includes more than the necessary number of CPUs and main memories (is made redundant) in order to improve its performance. This system LSI is considered to be a good product if at least one CPU and one main memory are normal. In this embodiment, the "system 150' has two CPUs 51 and 52, two main memories 53 and 54, a CPU 51 and 52 and a main memory 53 and 54".
A connection circuit (SWITCH) 55 that connects the connection circuit 4 as appropriate, and a connection information holding circuit (SWITCH) that controls the connection state of this connection circuit 55.
H-CTL) 56, a test auxiliary section 57 that assists in the execution of self-tests, a connection change circuit 58 that changes the contents of the connection information holding circuit 56, and a Test-ROM 59 that accommodates test means, ie, a test program. Here, FIG. 7 shows an example of a more specific configuration of this embodiment, focusing on an example of the configuration of the test auxiliary section, the connection circuit, the connection information holding circuit, and the connection change circuit.

The self-test procedure is almost the same as that explained in the embodiment shown in Figures 1 to 5, so here we will focus on how to connect the CPU and main memory based on the test results. This embodiment will be explained. In FIG. 7, the test auxiliary section 57 is constructed almost the same as the test auxiliary section 4 shown in FIG. 2, and similar parts are given the same reference numerals here.

The test auxiliary section 57 differs from the test auxiliary section 4 in FIG. 2 only in the following configuration. That is, a 4-input AND gate 61 is provided in place of the 3-input asodo gate 15 described above, and in addition to the same 3 inputs as the AND gate 15, an output st5 from a sequential circuit 68 of a connection change circuit 58, which will be described later, is also added. A signal obtained by inverting the output of the point a mentioned above and the output of an AND gate 65 of the connection change circuit 58, which will be described later, are applied to the reset terminal of the timer 14Z via an OR gate 62 in the form of a logical sum. In FIG. 7, the connection change circuit 58 delays the time Z window signal 12 so that the time window signal 12 rises later than the rise of the time over signal 13.
A delay line 64 with a delay time 63 for delaying the test mode designation signal 6, an AND gate 65 supplied with the inverted output of the test result display signal 7 from the flag 20 and the output from the delay line 63, the test mode signal 6 and the delay line a sequential circuit having an AND gate 66 supplied with an inverted output of the output from 64, an OR gate 67 receiving the AND outputs of AND gates 65 and 66, and a P terminal and an IJ set terminal, and generating outputs st, to st5. 68, and this connection change circuit 58 causes the test result display signal 7 to be “1”.
The connection state between the CPU and main memory is changed in a predetermined order until .

Here, the sequential circuit 68 connects the AND gate 65 to the P terminal.
Change its state from state 1 (assumed to be state 1 when reset) to state 5 by a signal from
Depending on each state, the outputs st, to st6 are output in the form shown in Figure 8 (in Figure 8, d is "1" or "0").
(indicates an arbitrary level that may be any one of the following), and its output is written to the connection information holding circuit 56, and any circuit may have any configuration as long as it holds such a function. The connection information holding circuit 56 shown in FIG.
Writing to these elements S, ~S4 is performed using the outputs st, ~st4 of the sequential circuit 68 of the connection change circuit 58.
and write command signal 6 which is the output of OR gate 67
9.

Although the connection circuit 55 in FIG. 7 is simplified here and shown with only AND gates 71 to 74, such a circuit is actually required for all signals.

Here, the output of the element S and the CPU 51 is connected to the asod gate 7.
1, the outputs of element S2 and CPU 52 are connected to AND gate 72.
In addition, the outputs of AND gates 71 and 72 are commonly connected in a wired-OR configuration and supplied to AND gates 73 and 74 at the next stage. and gate 73 and 7
The outputs of elements S3 and S4 are also added to 4. The outputs of AND gates 73 and 74 are coupled to main memories 53 and 54, respectively. In the connection circuit 55 having such a configuration, for example, if the sequential circuit 68 is in state 1, each element S, , S2, S3, and S4 of the connection information holding circuit 56
The outputs of are “1”, “0”, “1” and “0” respectively.
Therefore, through AND gates 71 and 73, the CPU
51 and the main memory 53 are connected. Te in Figure 7
It is assumed that the st-ROM 58 can be accessed from either the CPU 51 or the CPU 52, and its addressing is done in the same manner as in FIG. Next, the operation of the actuator in the embodiment of the present invention shown in FIG. 7 will be explained with reference to the time charts shown in FIGS. 9A to 9J.

In the following explanation, the CPU 52 and main memory 63 are normal;
It is assumed that the PU51 is defective. First, as shown in FIG. 9A, when the power is turned on, the potential at the middle point a of the time constant circuit 21 rises to 0 with a slight delay, so that the timer 14 and the program counter in the CPU (not shown) are activated by the test program. It is reset or initially set to indicate the start address. This point is similar to the embodiment described above with reference to FIGS. 1 to 5. Next, test mode designation signal 6
is applied and changes from "0" to "1" (see FIG. 9B), the delay line 64 and the AND gate 66 generate a positive pulse with a pulse width of 63 from the AND gate 66 as shown in FIGS. 9C and D. The sequential circuit 68 is reset to state 1 and zero. Further, the connection information corresponding to state 1 is written into the connection information holding circuit 56 by the above-mentioned positive pulse, that is, the write command signal 69 taken out from the OR gate 67, and at the same time, the output from the oscillator il is outputted from the oscillator il via the AND gate 61. It is transmitted to the CPU as a test clock.
A self-test is started with U51 and main memory 53 connected (state 1). Eventually, at the time when the self-test normally ends, the time window signal 12 is output from the timer 4 (see FIG. 9G), but as previously assumed, the CP
Since U51 is defective, the flag 20 is not set, and the test result display signal 7 remains at "0" as shown in FIG. 91. Subsequent time-over signal 13 (see Figure 9F)
As a result, the AND gate 61 is inhibited, the self-test clock supply is stopped, and the self-test in state 1 is therefore completed. After that, since the flag is "0", the time window signal 12 is delayed by the delay line 63 (see Figure 9).
is taken out from the AND gate 65 (see FIG. 9 J),
This resets the timer 14 and also resets the sequential circuit 68.
changes to state 2, and correspondingly, the connection information holding circuit 5
The contents of 6 will change. Furthermore, by resetting the timer 4, the time-over signal 13 changes from "1" to "0" as shown in FIG. Start self-test. In state 2, the CPU 62 and main memory 53 are connected. After going through the same process as described above, when the time window signal 12 is output, in this case, the C corresponding to the connection in state 2 is
Since PU52 and main memory 53 are normal, flag 20
is set and the test result display signal 7 changes from “0” to “1”
Changes to Therefore, the inverted signal of this signal and the delay line 63
The AND gate 65 output remains at "0", the timer 14 is not reset, and the time-over signal 13 also remains at "1". In this case, the system BI is determined to be non-defective and completes the self-test. Then, corresponding to this connection state, elements S,...
The contents of S2, S3, and S4 are held at 0, 1, 1, and 0, respectively, and since these elements S, through S4 are nonvolatile, this connection state is maintained even when the power is turned off. That is, this system 1 is connected in state 2 when shipped, and this connection state does not change under normal usage (test mode designation signal 6 is "0"). The above explanation takes as an example the case where the CPU 52 and the main memory 53 are normal, but if all the CPUs and main memories contain defects, all of the sequential circuits 68 corresponding to states 1 to 4 The above-mentioned self-test is executed for the connection status of , and the test result display signal 7 remains "0" for all of them, and the process in the first half of the time chart of FIGS. 9A to 9J is repeated. .

Next, the state of the sequential circuit 68 becomes state 5, and the output st5 of this sequential circuit 68 becomes "1", so even if the timer 14 is reset and the time-over signal 13 becomes "0", the AND gate 61 is prohibited. continues, and thereafter the oscillator 11
The output of is not transmitted to the CPU, completing the self-test.
The system LSI at this time is a defective product, which can be determined by the output of the test result display signal 7 being "0". Although the embodiment of the present invention in which the CPU and main memory are made redundant has been described above based on FIGS. 6 to 9, this is only one example of the present invention, and other configurations and test It can be easily assumed that the present invention can achieve functions essentially similar to those of the previous embodiments even if the method is used.

That is, in the present invention, a test auxiliary section, a connection change circuit, a connection information holding circuit, a connection circuit, and a Test-ROM having the above-mentioned functions are added to multiple CPUs and main memories and integrated on one chip. By configuring the system LSI, self-testing is possible, and a normal CPU and main memory can be automatically connected.This embodiment includes various modifications. Similar to the previous embodiment described in Figures 1 to 5, the self-test is not complete, so it may be necessary to perform a test by connecting it to a tester after the self-test. Also, in order to simplify the explanation, in this embodiment, the case where there are two CPUs and main memories and they are the unit of switching has been described, but if there are three or more CPUs and main memories, Alternatively, even if the unit of switching is a division of these, it is natural that the application can be applied by appropriately expanding and deforming the connection circuit, connection information holding circuit, and sequential circuit to cope with this. Still other embodiments of the present invention will be shown.

This is achieved by configuring the main memory in the first embodiment described above with reference to FIGS. 1 to 5 with a readable/writable memory element with an added function of permanently storing fixed data. A memory unit 80 that also serves as a CPU is connected to the CPUI. This type of memory element includes, for example, the latent image memory No. 1 published in 11335-1983, which can operate as either ROM or RAM depending on control information. This control information is stored in the memory unit 80 that has been
When set to 1, it operates as a ROM, and when set to 0, it operates as an RA.
Assuming that it works as M, how can this main memory and Tes
Let's explain how to operate the memory section 80 of the t-ROM, focusing on Z. The basic self-test procedure is the same as in the embodiments shown in FIGS. 1 to 5, so the explanation will be omitted here. FIG. 11 shows a part of the test auxiliary section and the memory section, focusing on changes from FIG. 2, and all parts not shown here have the same configuration as FIG. 2.

The configuration within the broken line block in the figure is an additional circuit to that in FIG. 2. That is, this example has a JK flip-flop 81, with "1" at its J and K terminals, the output of the AND gate 18 at its clock terminal C, and a reset terminal 81R.
The inverted signal of the point a output of the time constant circuit 21 is added to each of the points. The Q output of JH flip-flop 81 and the AND output of AND gate 18 are applied to AND gate 82, and the Q output of JK flip-flop 81 and the AND output of AND gate 18 are applied to AND gate 83. and gate 8
2 is applied to an OR gate 85 via a delay line 84 with a delay time of 64. This delay time 64 is set so that the delay line output rises later than the time-over signal 13. The OR gate 85 includes a time constant circuit 21
The OR output of the OR gate 85, which also adds the inverted signal of the output at point a, is applied to the reset terminal 14R of the timer 14 and also to the initial set terminal 27 of the CPU 1. The output of the AND gate 83 mentioned above is applied to the set terminal of the flag 20. The memory section 80 is divided into two areas 80A and 80B with addresses 0 to An-. and addresses An to A2n-., each having the control information terminals Co and C, respectively.

Furthermore, both areas 80A and 80B' are run by the same test program (which may be similar to that shown in FIG. 4).
Write it as M. The Q and Q outputs of the JK flip-flop 81 are supplied to control information terminals Co and C of the memory section 80, respectively. Furthermore, the Q output of the JK flip-flop 81 and the highest bit of the address stored in the program counter in the CPUI are combined with an exclusive OR circuit 86, and the exclusive OR output is sent to each area 80A of the memory section 80 and In addition to 80B, the highest bit of each address is inverted, the details of which will be described later.
Next, time charts for explaining the operation of FIG. 11 are shown in FIGS. 12A to 12H'.

First, the Q output of the JK flip-flop 81 is “
0” (see Figure 12B), Co=“0”, C
,="1", that is, the area 80A at addresses 0 to An- is RAM, and the area 808 at addresses An to A2n- is RO.
It operates as M. Therefore, addresses An~A2n-,
The CPUI and the area 80A at addresses 0 to An- of the memory section 80 are tested by the test program. If the result of this self-test is normal, the AND gate 18 outputs a positive pulse of 0 as shown in FIG. 12A through the same configuration as in FIG. 2, and as shown in FIGS. 12D and F. This positive pulse resets the timer 14 through the AND gate 82 and delay line 84 through the OR gate 85, and the CPU
Set the program counter in I to the start address An of the test program. At the same time, timer 14
By being reset, the time-over signal 13 changes from "1" to "0" (see FIG. 12E), and the self-test starts again. At this point, the output of the AND gate 18 causes the Q of the JK flip-flop 81 to be
C because the output is 0 “1”. ="1",C,=
"0'', the area 80A from address 0 to An-, is ROM, and the area 80B from address An to A2n- is RA.
It becomes M. That is, a self-test of the CPUI and the address An to A2n- of the memorizer section 80 and the area 80B is started by the test program for the address 0 to An- and the area 80A. If this self-test also ends normally, the CPUI and all areas of the memory section 80 are normal, and therefore the system LSI is a good product, and as shown in FIG. Flag 20 will be set. The exclusive OR circuit 86 shown in FIG. 11 is for inverting the highest bit of the address during the latter half of the self-test described above. In this circuit, when the program counter in the CPUI is initially set, it is always set to indicate address An, so in order to use the contents of address 0 to An-, area 80A as a test program, the address must be converted. It is necessary because it is necessary. Note that depending on the main memory capacity, it is not sufficient for this conversion to simply invert the highest bit of the address, and it is natural that a certain amount of conversion is required. 'It is necessary to configure this with a separate circuit. As explained above, when the memory unit 80 is used as the main memory and Test-ROM, it is necessary to perform a self-test using two combinations: the first half of the CPU and main memory, and the second half of the CPU and main memory. .

The above explanation is based on the first embodiment (Figs. 1 to 5).
This is a case where the main memory 2 is also used as the Test-ROM 3, but this dual-use form is similar to the second embodiment (6th embodiment).
It is obvious that it can be applied in almost the same way to the cases shown in FIGS. in this way,
If the Test-ROM and the main memory are used together, the amount of hardware required just for self-testing can be greatly reduced, and this effect is extremely large. In the above embodiments, the explanation has been made on the assumption that the test auxiliary section and the Test-ROM are normal by performing a test in advance, but if these contain defects, the self-test becomes completely ineffective.

The embodiment shown in FIG. 13 solves this problem.
The st-ROM has an error correction circuit 9 such as a Hamming check.
0 is added, and 3 for test auxiliary part 4 is, for example, 3.
The structure is such that errors can be masked by multiplying the signals and taking a majority vote by the majority logic circuit 91. Since it is obvious that this type of error detection function can be added to the second embodiment described above, description 3 of its application example will be omitted here. As explained above, according to the present invention, in realizing an information processing system consisting of a main memory and a CPU on one chip, four means for testing each function of the information processing system are simultaneously installed on the chip.
Since it is also equipped with the following functions, it is possible to independently perform a test (self-test) within one chip without using a tester, which has the advantage of making it possible to significantly reduce test costs.

Moreover, it not only provides means for installing more than the necessary number of CPUs and main memories in the information processing system described above and testing each function, but also means for sequentially changing the connection state between each CPU and main memory according to the test results. Since these are also provided on the same chip, there is an advantage that it is possible not only to perform a self test but also to automatically connect a normal CPU and main memory without using a tester.

Furthermore, in the present invention, the main memory includes a latent image memory (
By using something like Hakama Gansho 53-11335), this can also function as a memory to house the test procedure, reducing the amount of hardware needed just for the self-tests mentioned above. It is also possible to do so.

Moreover, by adding an error correction function or an error mask function to a part required only for self-testing, there is an advantage that the need to test this part in advance is reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the concept of one embodiment of the information processing system integrated circuit of the present invention, FIG. 2 is a block diagram showing an example of a detailed configuration focusing on the configuration of the test auxiliary section in FIG. 1, FIG. 3 is a diagram showing addressing of the main memory and Test-ROM, FIG. 4 is a flowchart showing an example of a test program flowchart, and FIG. 5 is a flowchart showing an example of a test program flowchart. A time chart showing the signals, FIG. 6 is a block diagram showing an embodiment of the present invention when more than the necessary number of CPUs and main memories are installed (in case of redundancy), and FIG. 8 is a block diagram showing an example of the detailed configuration of the figure, FIG. 8 is a diagram showing the state of the sequential circuit and its output, and FIGS. 9 A to J are time charts showing signals of each part for explaining the operation of FIG. 7. , FIG. 10 is a block diagram showing an embodiment of the present invention having a configuration in which both the main memory and Test-ROM are used, FIG. 11 is a block diagram showing an example of the detailed configuration of FIG. 10, and FIG. 12 Figures A through 11 are time charts showing the signals of each part for explaining the operation, and Figure 13 shows an embodiment of the present invention in which error correction or error masking functions are added to parts necessary only for self-tests. FIG. 1...CPU, 2...Main memory, 3.
...Test-ROM, 4...Test auxiliary section, 5...System LSI, 6...Test mode designation signal, 7...Test result display signal, 1
1... Oscillator, 12... Time window signal, 13... Time over signal, 14...
...Timer, 14R...Reset terminal, 15
, 16, 17, 18...And gate, 19...Delay line, 20...Flag, 21...Time constant circuit, R...Resistor, C...Capacitor, V ……power supply,
22...Clock input terminal, 23...
Or gate, 24... Normal clock, 25...
... Self-test clock, 26 ... Test designation terminal, 27 ... Initial set terminal, 28 ... Test result terminal, 50. ．． …． System LSI, 5 1,
52. ．． ．． ... CPU, 53, 54 ... Main memory, 55 ... Connection circuit, 56 ... Connection information holding circuit, 57 ... Test auxiliary section, 58 ...・
Connection change circuit, 59...Test-ROM, 6
1, 65, 66...and gate, 62, 67...
...or gate, 63,64...delay line,
68...Sequential circuit, 69...Write command signal, 71, 72, 73, 74...And gate,
80...Memory section, 80A...Address 0~An-
, area, 80B...address An~A2n-,
Area, 81...JK flip-flop, 81R
...Reset terminal, 82, 83...AND gate, 84...Delay line, 85...OR gate, 86...Exclusive OR circuit, 90... Error correction circuit, 91...majority logic circuit. Figure 1 Figure 3 Figure 4 Figure 2 Figure 5 Figure 6 Figure 8 Figure 10 Figure 11 Figure 7 Figure 9 Figure 12 Figure 13

Claims (1)

[Claims] 1. An information processing system consisting of a main memory that stores programs and data, and a central processing unit that performs various calculations and controls based on the contents of the main memory, and a test of the normality of the information processing system. The information processing system, the fixed memory, and the test are provided with a fixed memory that records the procedure for performing the test, and a test auxiliary means that executes the test according to an external test mode designation and outputs the test result to the outside. auxiliary means are integrated on one chip, the central processing unit and the main memory are installed in a larger number than necessary for redundancy, and the connecting circuit connects the central processing unit and the main memory as appropriate. , a connection information holding circuit made of a rewritable nonvolatile element that controls the connection state of the connection circuit, and a connection information changing means for changing the contents of the connection information holding circuit based on the test result. Information processing system integrated circuit. 2. The information processing system integrated circuit according to claim 1, wherein the main memory is composed of a readable/writable memory element with an added function of permanently storing fixed data, and An information processing system integrated circuit characterized in that it is configured to double as a fixed memory. 3. In the information processing system integrated circuit according to claim 1 or 2, the fixed memory, the test auxiliary means, the connection information holding circuit, and the connection information changing means are error-corrected. An information processing system integrated circuit characterized in that it is configured with an additional function or an error masking function.