JPS60165732A - Film carrier lsi - Google Patents
Film carrier lsiInfo
- Publication number
- JPS60165732A JPS60165732A JP59021452A JP2145284A JPS60165732A JP S60165732 A JPS60165732 A JP S60165732A JP 59021452 A JP59021452 A JP 59021452A JP 2145284 A JP2145284 A JP 2145284A JP S60165732 A JPS60165732 A JP S60165732A
- Authority
- JP
- Japan
- Prior art keywords
- holes
- lsi
- film
- arrays
- film carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
く技術分野〉
本発明はフィルム・キャリアＬＳＩに関するものである
。[Detailed Description of the Invention] Technical Field> The present invention relates to a film carrier LSI.
〈従来技術〉
従来のフィルム・キャリアＬＳＩにおいては、第１図に
示すように、フィルム１の巻き取り方向（図に於いて、
矢印で示す）に対し平行にＬＣＤ等への圧着パターン（
入出力信号用端子列）２を配置し、第１図中、点線によ
り示す形状にカットし、製品に実装していた。なお、第
１図に於いて、３はスプロケット穴、４は製品に実装す
るときのガイド穴、５は電源供給用パターン（電極）、
６はＬＳＩチップ・モールド部である。<Prior art> In a conventional film carrier LSI, as shown in FIG.
The crimp pattern (indicated by the arrow) on the LCD etc. is parallel to the
A terminal row for input/output signals) 2 was arranged, cut into the shape shown by the dotted line in FIG. 1, and mounted on the product. In Fig. 1, 3 is a sprocket hole, 4 is a guide hole for mounting on a product, 5 is a power supply pattern (electrode),
6 is an LSI chip mold section.
しかしながら、第１図に示す従来の構成ではフィルム単
位長さあたりのＬＳＩの取り数をあまり多くすることが
できないという問題点があった。However, the conventional structure shown in FIG. 1 has a problem in that the number of LSIs per unit length of film cannot be increased very much.
すなわち、第１図に示す従来の構成でＬＳＩチップ間の
距離を短くすれが、それだけ取り数を多くすることがで
きるが、あまり距１ＩＩＩＦｆ：短くすれば、入出力信
号用端子列２の端子ピッチが細かくなり、実装が困難と
なる。In other words, if the distance between LSI chips is shortened in the conventional configuration shown in FIG. 1, the number of chips can be increased accordingly. becomes detailed and difficult to implement.
〈発明の目的・構成〉
本発明は上記従来の問題点を解決することを目的として
なされたものであり、入出力信号用端子列をフィルムの
幅方向に配置し、更に、スプロケット穴を機器への実装
時のガイド穴として使用する構成とすることにより、Ｌ
ＳＩの取り数増加をはかり、これによって大幅なコスト
・ダウンを達成したフィルム・キャリアＬＳＩを提供す
るものである。<Objective/Structure of the Invention> The present invention has been made with the aim of solving the above-mentioned problems of the conventional art, and includes arranging terminal rows for input/output signals in the width direction of the film, and furthermore, connecting sprocket holes to equipment. By configuring it to be used as a guide hole when mounting the L
The present invention aims to increase the number of SIs and thereby provide a film carrier LSI that achieves a significant cost reduction.
〈実ｆｈＬ例〉
以下、実施例に基づいて本発明の詳細な説明する０
第２図に本発明の一実施例を示す。図に於て、１１はフ
ィルム、１２は入出力信号用端子列、１３はスプロケッ
ト穴、Ｉ４は電源供給用パターン（電極）、１５はＬＳ
Ｉチップ・モールド部である。そして、第２図中、点線
１６により示す形状に打抜く。<Actual fhL Example> Hereinafter, the present invention will be described in detail based on an example. FIG. 2 shows an example of the present invention. In the figure, 11 is the film, 12 is the input/output signal terminal row, 13 is the sprocket hole, I4 is the power supply pattern (electrode), and 15 is the LS
This is the I-chip mold part. Then, it is punched out into the shape shown by the dotted line 16 in FIG.
図に示すように、ＬＣＤ等への圧着パターンす
（入出力信号用端子列）１２を、フィルム１１０巻き取
り方向（図に於て、矢印で示す）に対し直角に、すなわ
ちフィルム１１の幅方向に配置し、また、フィルム・キ
ャリア送りの為に設けられているスプロケット穴１３を
製品実装時にガイド穴として利用する構成とすることに
より、フィルムの有効利用を図り、ＬＳＩの取り数を増
加させて、コストダウンを行なおうとするものである。As shown in the figure, the crimp pattern (terminal row for input/output signals) 12 on the LCD etc. is perpendicular to the winding direction of the film 110 (indicated by an arrow in the figure), that is, in the width direction of the film 11. In addition, the sprocket hole 13 provided for transporting the film carrier is used as a guide hole during product mounting, thereby making effective use of the film and increasing the number of LSIs. This is an attempt to reduce costs.
重重への実装例を第３図に示す。第３図＋ａｌは上方よ
り見た配置図であり、第３図（ｂ）は断面図である０
第２図に示す形状に打抜いたフィルム・キャリアＬＳＩ
２１は、第３図に示す状態に実装し、キーシート２２を
利用し、圧着ゴム２３を用いてＬＣＤ２４に圧着接続す
る。この時、フィルム・キャリアに当初より設けられて
いるスプロケット穴１３の中の一部１３−１利用し、キ
ャビネット２５に位置決めする。す力わち、キャビネッ
ト２５にボス２６を設け、このボス２６と」−記スプロ
ケット穴１３−１との底台によって上記位置決めを行な
う。Figure 3 shows an example of implementation in a heavy vehicle. Figure 3+al is a layout diagram seen from above, and Figure 3(b) is a cross-sectional view of the film carrier LSI punched into the shape shown in Figure 2.
21 is mounted in the state shown in FIG. 3, and is crimped and connected to the LCD 24 using a key sheet 22 and a pressure bonding rubber 23. At this time, the film carrier is positioned in the cabinet 25 by using a portion 13-1 of the sprocket hole 13 originally provided in the film carrier. In other words, the cabinet 25 is provided with a boss 26, and the above positioning is performed by the bottom of the boss 26 and the sprocket hole 13-1.
電源供給用パターン１４は、板バネ等より成る電池端子
２７により太陽電池等の電源２８に接続される。The power supply pattern 14 is connected to a power source 28 such as a solar cell through a battery terminal 27 made of a plate spring or the like.
なお、第３図において、２９はキートップ、３０は底パ
ネル、３１はキ一部押え板である。In FIG. 3, 29 is a key top, 30 is a bottom panel, and 31 is a key holding plate.
ＬＳＩの打抜き形状は、第４図に示すような単純な長方
形状とＩ〜でもよい。しかし、そのように今≠呟ると、
位置決めに使用できるスプロケット穴がなくなる場合が
ある。すなわち、第３図の場合で考えれば理解しやすい
が、ＬＣＤや太陽電池の電池端子等があるために、位置
決め用のボスを立てることができなくなる。また、第５
図に示す如く、ハツチング部分を捨てるならば、第３図
のような場合も使用できるが、この場合は、単位長あた
りのＬＳＩの取り数が減少する。The punched shape of the LSI may be a simple rectangular shape as shown in FIG. 4 or I~. However, if I mumble like that now,
There may be no sprocket holes available for positioning. That is, although it is easy to understand if you consider the case of FIG. 3, it becomes impossible to erect a boss for positioning because of the presence of battery terminals for the LCD and solar cells. Also, the fifth
If the hatched portion is discarded as shown in the figure, the case shown in FIG. 3 can also be used, but in this case, the number of LSIs per unit length is reduced.
上記実施例のようなＯ形状には、そのよ穴間ｈｔ点がな
いものである。The O-shape as in the above embodiment does not have ht points between the holes.
〈発明の効果〉
以上詳細に説明したように、本発明によれば、入出力信
号用端子列の端子ピンチをそれ程細かくすることなく、
ＬＳＩチップ間の距離ヲ短くすることができるので、Ｌ
ＳＩの取り数を大幅に増加させることができ、大きなコ
スト・ダウンとなるものである。<Effects of the Invention> As explained in detail above, according to the present invention, the terminal pinch of the input/output signal terminal row can be reduced without making it too fine.
Since the distance between LSI chips can be shortened, L
The number of SIs available can be greatly increased, resulting in a significant cost reduction.
第１図は従来のフィルム・キャリアＬＳ Ｉ’に示す斜
視図、第２図は本発明に係るフィルム・キャリアＬＳＩ
を示す斜視図、第３図は本発明に係るフィルム・キャリ
アＬＳＩの実装状態を示す図であり、同図（ａ）は上方
より見た配置図、同図（１））は断面図、第４図及び第
５図は本発明の他の実施例の説明に供する平面図である
。
符号の説明
１１：フィルム、１２：入出力信号用端子列、Ｌ（（１
Ｂ−１）：スプロケット穴、１４：電源供給用パターン
、１５：ＬＳＩチップ・モールド部、１６：ＬＳＩ打抜
き形状を示す点線、２１：フィルム・キャリアＬＳＩ、
２５：キャビネット、２６：ボス。FIG. 1 is a perspective view of a conventional film carrier LSI', and FIG. 2 is a perspective view of a film carrier LSI according to the present invention.
FIG. 3 is a perspective view showing the mounting state of the film carrier LSI according to the present invention, FIG. 3(a) is a layout view seen from above, FIG. 4 and 5 are plan views for explaining other embodiments of the present invention. Explanation of symbols 11: Film, 12: Input/output signal terminal row, L ((1
B-1): Sprocket hole, 14: Power supply pattern, 15: LSI chip mold part, 16: Dotted line indicating LSI punching shape, 21: Film carrier LSI,
25: Cabinet, 26: Boss.
Claims (1)
用端子列全フィルムの幅方向に配置し、更に、スズロケ
ット穴を機器実装時のガイド穴とする構成としたことを
特徴とするフィルム・キャリアＬＳＩ。1. A film carrier LSI characterized in that terminal rows for input/output signals are arranged in the width direction of the entire film, and the tin rocket holes are used as guide holes when mounting devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59021452A JPS60165732A (en) | 1984-02-07 | 1984-02-07 | Film carrier lsi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59021452A JPS60165732A (en) | 1984-02-07 | 1984-02-07 | Film carrier lsi |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60165732A true JPS60165732A (en) | 1985-08-28 |
| JPH0365659B2 JPH0365659B2 (en) | 1991-10-14 |
Family
ID=12055352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59021452A Granted JPS60165732A (en) | 1984-02-07 | 1984-02-07 | Film carrier lsi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60165732A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7073254B2 (en) | 1993-11-16 | 2006-07-11 | Formfactor, Inc. | Method for mounting a plurality of spring contact elements |
| US6483328B1 (en) | 1995-11-09 | 2002-11-19 | Formfactor, Inc. | Probe card for probing wafers with raised contact elements |
| US6468098B1 (en) | 1999-08-17 | 2002-10-22 | Formfactor, Inc. | Electrical contactor especially wafer level contactor using fluid pressure |
| US7396236B2 (en) | 2001-03-16 | 2008-07-08 | Formfactor, Inc. | Wafer level interposer |
-
1984
- 1984-02-07 JP JP59021452A patent/JPS60165732A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0365659B2 (en) | 1991-10-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |