JPS601660B2 - Storage device memory content destruction prevention device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is provided with a storage device, in which a method for processing each input is stored in the form of a program, which is a set of instructions, and in response to an external input, according to the program. The present invention relates to a storage content destruction prevention device for a storage device, which is suitable for use in a stored program type sequence control device that sequentially controls controlled objects.

Such a sequence control device generally has a program storage device that stores programs and a data storage device that stores data.

Program storage devices use non-volatile devices, such as core memory, but data storage devices generally use volatile devices constructed from low-cost, low-power-consuming semiconductor integrated circuits. . Therefore, the stored contents of the data storage device may be destroyed due to a power failure such as a power outage or a power failure. Therefore, the range of data that can be stored in the data storage device is limited, and there is a danger in terms of control when storing data that cannot be destroyed. Therefore, if a situation arises in which you have to handle data that cannot be destroyed, use the free space of a non-volatile program storage device as part of the data storage device, and store such data here. One possibility is to store data. However, this results in the inconvenience that the processing device becomes complicated, and each part also becomes complicated accordingly. Also, if an abnormality occurs in the power supply,
By storing the memory contents of the data storage device in a nonvolatile storage device, the range of data that can be stored in the data storage device can be considerably expanded, and the data storage device can be used more effectively. However, the control power supply for a storage device is made by converting an AC power supply to a DC power supply. Therefore, the voltage of this control power source does not drop instantaneously even when the AC power supply is cut off or interrupted, but drops for a while with a certain time constant due to the storage effect of, for example, a capacitor in the DC converting circuit. In such a transient state, the operation of the control circuit becomes unstable, and unnecessary read or write current may flow into the storage device, which may destroy the written contents. For this reason, conventionally, a power supply abnormality detector has been built into the sequence control device, and if there is an abnormality in the power supply, a prohibition signal that prohibits reading or writing to the storage device is immediately applied. Therefore, in the conventional system, there is no time to transfer the contents of the data storage device to a non-volatile storage device after a power failure occurs, and such data protection operations are impossible. The power supply for driving the storage device or the control power supply for driving the control circuit that performs reading and writing is produced by converting an alternating current power supply to a direct current, as described above.

Furthermore, these power supplies require considerable stability.
Therefore, for example, a capacitor of a fairly large capacity is used in the DC conversion circuit, and the time constant is extremely large. Therefore, even if a power failure occurs such as a power outage or a power outage, the DC conversion circuit will stably output the specified voltage that normally operates the storage device or its control circuit for a certain period of time, and then While outputting voltage, the output voltage gradually drops. The time period during which the DC conversion circuit can continue to output the specified voltage after the power supply becomes abnormal, that is, the specified voltage output time during abnormality, can be known in advance when setting the DC conversion circuit. The present invention has been made in order to solve the above-mentioned drawbacks by effectively utilizing the specified voltage output time during abnormality of this DC conversion circuit, and has a simple configuration that prevents the power supply abnormality detection circuit from generating an abnormality. It is an object of the present invention to provide a device for preventing storage contents from being destroyed in a storage device, which can generate a prohibition signal for prohibiting reading and writing to the storage device after a scheduled time, and has general versatility.

In order to achieve the above object, the present invention is characterized by a clock pulse generator that generates a clock pulse for incrementing a program counter that sequentially specifies each address of a storage device, and a Alternatively, a power supply abnormality detection circuit that detects a power outage and outputs an abnormal signal, and a predetermined setting value corresponding to the time during which predetermined storage contents of the volatile storage device can be transferred to the nonvolatile storage device, are connected to the abnormality signal. and starts counting the clock pulses by inputting clock pulses from the clock pulse generator and receiving the abnormal signal;
The present invention further includes a preset counter that outputs a control signal when the count reaches the set value, and the control signal inhibits reading and writing of the storage device.

An embodiment of the present invention shown in FIG. 1 will be described below.

Reference numeral 1 designates a clock pulse generator that generates clock pulses for incrementing a program counter that sequentially specifies each address in the storage device.

AC is an alternating current main power source, and 2 is a power supply abnormality detection circuit that detects a short cut or power outage of the alternating current main power source AC and generates an abnormal signal. 3 is a counting circuit, and the case where a preset counter is used is shown as an example.

This preset counter 3 is configured to input an output signal a from the power supply abnormality detection circuit 2 to a preset terminal Pr, and input this signal to a clear terminal CL via a negative circuit N. Therefore, this counter 3 is always cleared, and when the power supply abnormality detection circuit 2 outputs an abnormality signal, the time setting value f is preset. Furthermore, this counter 3 inputs the clock pulse from the clock pulse generator 1 through an AND circuit A to its input terminal IN'. The AND circuit A is controlled to open and close using a signal obtained by negating the output from the carry terminal C by a negation circuit N2. 4 is a power supply reset circuit, which detects the rise of the DC power supply Vcc with a product circuit consisting of a resistor R and a capacitor C, and resets the accumulator, various registers, flip-flops, etc. of the sequence control device for a certain period of time from the time the power is turned on. A reset signal CS is generated.

Q is a transistor that forms the discharge circuit of the capacitor C. When a carry signal is generated from the terminal CO of the preset counter 3, this transistor Q becomes conductive and forcibly discharges the charge of the capacitor C, and resets the power supply. Circuit 4 outputs a reset signal CS. Reference numeral 5 denotes a flip-flop circuit, which is reset by the output of the power supply reset circuit 4, and whose output Q is applied to an operation inhibit terminal for inhibiting reading and writing of the memory device M via a negative circuit N3.

Reference numeral 6 denotes a latch relay, which is used to guarantee the operation inhibition signal of the storage device M.

That is, after a certain period of time has elapsed after the AC main power supply AC is interrupted or interrupted, the output voltage Vcc of the DC conversion circuit becomes unstable. At this point, the output of the NOT circuit N3 can no longer maintain the operation inhibit signal at the expected level. The latch relay 6 guarantees the operation prohibition signal at the expected level at this time.
Contact C' is in a floating state, and contact C2 is grounded. The neutral point C3 is connected to the operation inhibit terminal of the storage device M. L,,L are coils, when the coil L is excited, the neutral point C3 and the contact C, are connected, and when the coil L is excited, the neutral point C3 and the contact C2 are connected; Remains connected until energized. One end of each of the coils L and L2 is connected to the DC power supply Vcc, and the other end of the coil L is connected to the output end of the AND circuit A2.
The other end is connected to the output end of AND circuit A3. AN
The D circuit A2 is configured to receive the output signal of the power supply reset circuit 4 and a signal obtained by negating the output of the power supply abnormality detection circuit 2 by a negation circuit N4. The AND circuit A3 is configured to receive a signal obtained by negating the output signal of the power supply reset circuit 4 by a negation circuit N5. FIG. 2 shows waveforms of various parts of the circuit shown in FIG. 1, where AQ shows the voltage waveform of the AC main power supply AC, and VCC shows the voltage waveform of the DC power supply VCC.

a, b, and CS indicate output waveforms of the power supply abnormality detection circuit 2, preset counter 3, and wire reset circuit 4. d shows a waveform applied to the operation inhibit terminal of the storage device M. Below, the second
The operation shown in FIG. 1 will be explained with reference to the drawings.

First, when the power is turned on, the power supply reset circuit 4
It detects the rising edge of c and outputs a logical "0" reset signal for a certain period of time. This reset signal resets the accumulator, various registers, flip-flops, etc. of the sequence control device. At the same time, this reset signal resets the flip-flop circuit 5. Then, the output terminal Q of the flip-flop circuit 5
outputs a logical "1" signal, and the output of the NOT circuit N3 becomes logical "0", prohibiting reading and writing of the memory device M. At this point, the power supply AC is normal, and the power supply abnormality detection circuit 2 outputs a logical "1" signal. Therefore, since the pret counter 3 is cleared, no carry signal is output from the carry terminal C, the AND circuit A closes its gate, and no clock pulse is input. Also, the output of the power supply abnormality detection circuit 2 is logically “1” and the output of the power supply reset circuit 4 is logically “0”.
”, the output of AND circuit A2 is logically “
1”, the output of AND circuit A3 becomes logically “0”,
The coil L2 is excited, the neutral point C3 is grounded, and a logical "0" inhibit signal is applied to the operation inhibit terminal of the storage device M. After a certain period of time, the power supply reset circuit 4 logically
When a signal of "1" is output, the output of the negative circuit N2 is logically "1", the coil L of the latch relay 6 is energized, and the prohibition signal applied to the memory device M is released.Next, at the time of to, the AC main power supply is Suppose that the power supply is stopped due to AC interruption or power outage. However, for the reason mentioned above, the DC power supply Vcc outputs the specified voltage for the specified abnormal output time To from the time to.At the time to, the AC mains power supply is stopped. When an abnormality occurs in the power supply AC, the power supply abnormality detection circuit 2 detects this and outputs a logical "0" abnormality signal after a detection delay time.
This signal causes the blit counter 3 to preset the time setting value f. At the same time, the carry terminal CO is logically “
0" signal, and the NOT circuit N2 logically outputs a "0" signal to open the AND circuit A. As a result, the clock pulse from the clock pulse generator 1 is applied to the input terminal IN of the preset counter 3. However, the output of the power supply reset circuit 4 remains unchanged, the latch relay 6 also maintains the above state, the signal to the storage device M becomes logically "1", and the prohibition signal is released. Since the AND circuit A is opened, the preset counter 3 counts the clock pulses from the clock pulse generator 1. After a certain period of time Tc, when the count content of the preset counter 3 reaches the time set value f, the carry terminal C is opened. A logical ``1'' signal is output from .As a result, the NOT circuit N2 outputs a logical ``10'' signal, closing the AND circuit A, and prohibiting the input of clock pulses to the preset counter 3. do. At the same time, this carry signal is applied to the power supply reset circuit 4, conducts the transistor Q, and discharges the charge of the capacitor C, so that the power supply reset circuit 4 outputs a logic "0" reset signal after a predetermined delay time. Output. The flip-flop circuit 5 is reset by this reset signal,
A logical "1" signal is output from the output terminal Q. This output is negated by the negation circuit N3, and an operation prohibition signal of logical "0" is applied to the operation prohibition terminal of the storage device M.
Since the power supply abnormality detection circuit 2 outputs a logical "0" signal and the power supply reset circuit 4 outputs a logical "0" signal, the output of the AND circuit A3 is logically "1", and the output of the AND circuit A3 is It becomes logically "0", the excitation of the coil L is canceled, and the coil L is excited.

As a result, the neutral point C3 is grounded, and a stable operation prohibition signal of logical "0" is applied to the operation prohibition terminal of the storage device M. In this way, the operation prohibition signal can be applied to the storage device M after a certain period of time Tc after the AC main power supply AC becomes abnormal. Moreover, since the specified abnormality voltage output time To can be known in advance at the design stage of the DC conversion circuit, if the time Tc is within the range of this time To,
Can be set in advance. Therefore, it is possible to interrupt the processing operation of the sequence control device by an abnormality signal from the power supply abnormality detection circuit 2, and store the contents of the data storage device in a non-volatile, for example, empty area of a program storage device within this time Tc. Since it is possible to store even data that would be difficult to destroy in a data storage device, the scope of use of the data storage device can be greatly expanded. Moreover, this time T
If c is within the specified voltage output time during abnormality, the time setting value f
It can be arbitrarily selected by changing . Therefore, application to control power supplies with different specifications can be easily handled by changing the set value of the print counter. In other words, it becomes possible to use the present invention for general purposes in control power supplies having various specifications. Since this time Tc is managed by a clock pulse generator that generates clock pulses for incrementing the address counter, it is extremely accurate and can be synchronized with each part of the sequence control device, which is extremely convenient. It is. As is clear from the above description, according to the present invention, with a simple configuration, after a certain period of time after the power supply abnormality detection circuit generates an abnormal signal,
It is possible to obtain a storage content destruction prevention device for a storage device that can apply an operation prohibition signal to an operation prohibition terminal of the storage device.

Therefore, the contents of a volatile data storage device can be evacuated into a nonvolatile storage device in the event of a power failure;
The scope of use of data storage devices can be greatly expanded. Furthermore, since the operation prohibition signal can be reliably applied to the storage device after a certain period of time, the contents of the storage device can be reliably protected. In addition, the time from when a power failure occurs until reading and writing to the storage device is prohibited can be easily handled by changing the setting value of the preset counter, so it can be used universally for control power supplies with various specifications. Is possible.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
It is a figure which shows the waveform of each part of a figure. 1: Clock pulse generator, 2: Power supply abnormality detection circuit, 3
: Counting circuit, AC: AC main power supply. Younger brother/Figure 2

Claims (1)

[Claims] 1. A clock pulse generator that generates a clock pulse for incrementing a program counter that sequentially specifies each address in a storage device, and a power supply abnormality detection circuit that detects interruptions or power outages in the AC main power supply and outputs an abnormality signal. , preset a predetermined setting value corresponding to the time during which predetermined storage contents of the volatile storage device can be transferred to the nonvolatile storage device in response to the abnormal signal, and also preset the clock pulse from the clock pulse generator. a preset counter that starts counting the clock pulses upon receiving the abnormal signal and outputs a control signal when the count reaches the set value; A storage content destruction prevention device for a storage device that prohibits writing.