JPS60169933U - semiconductor circuit - Google Patents

semiconductor circuit

Info

Publication number
JPS60169933U
JPS60169933U JP5827484U JP5827484U JPS60169933U JP S60169933 U JPS60169933 U JP S60169933U JP 5827484 U JP5827484 U JP 5827484U JP 5827484 U JP5827484 U JP 5827484U JP S60169933 U JPS60169933 U JP S60169933U
Authority
JP
Japan
Prior art keywords
channel mis
source
resistor
transistor
power source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5827484U
Other languages
Japanese (ja)
Inventor
雅司 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5827484U priority Critical patent/JPS60169933U/en
Publication of JPS60169933U publication Critical patent/JPS60169933U/en
Pending legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は相補型絶縁ゲート型電界効果トランジスタを用
いた従来のCR発振器の構成を示す回路図、第2図aは
本考案の第1の実施例を示す回路図、第2図すはその各
部の電圧、電流の関係図、第3図は本考案の第2の実施
例を示す回路図である。 1.1′・・・入力、2,2′・・・出力、3,4・・
・コンパレータ、5・・・フリップフロップ、11・・
・入力、12・・・出力、13.14・・・電源、15
. 16. 17・・・インバータ、co・・・容量、
Ro、 R1,R2,R3−・・抵抗、QNO? QN
O’? QNI ? QN2 ””Nチャネル絶縁ゲー
ト型電界効果トランジスタ、Qpl g Qp2・・・
Pチャネル絶縁ゲート型電界効果トランジスタ。
FIG. 1 is a circuit diagram showing the configuration of a conventional CR oscillator using complementary insulated gate field effect transistors, FIG. 2a is a circuit diagram showing the first embodiment of the present invention, and FIG. FIG. 3 is a circuit diagram showing a second embodiment of the present invention. 1.1'...input, 2,2'...output, 3,4...
・Comparator, 5...Flip-flop, 11...
・Input, 12... Output, 13.14... Power supply, 15
.. 16. 17...Inverter, CO...Capacity,
Ro, R1, R2, R3-...Resistance, QNO? QN
O'? QNI? QN2 ""N-channel insulated gate field effect transistor, Qpl g Qp2...
P-channel insulated gate field effect transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1、第2のPチャネル型MISトランジスタと第1、
第2のNチャネル型MISトランジスタと直列接続され
第1と第2の電源間に接続された第1、第2、第3の抵
抗を含み、前記第1のPチャネル型MIS )ランジス
タと前記第1のNチャネル型MISトランジスタのゲー
ト及びドレインはそれぞれ共通接続されて入力及び出力
を形成し、前記第2のNチャネル型MISトランジスタ
のソースは前記第1のPチャネル型MISトランジスタ
のソースにドレインは前記第1の電源にゲートは前記第
1の抵抗と前記第2の抵抗の接続点もしくは前記第1の
電源にそれぞれ接続され、前記第2のPチャネル型MI
Sトランジスタのソースは前記第1のNチャネルMIS
トランジスタのソースにドレインは前記第2の電源にゲ
ートは前記第2の抵抗と前記第3の抵抗との接続点もし
くは前記第2の電源にそれぞれ接続されて成ることを特
徴とする半導体回路。
first and second P-channel MIS transistors;
The first P-channel MIS transistor includes first, second, and third resistors connected in series with the second N-channel MIS transistor and connected between the first and second power supplies. The gate and drain of the first N-channel MIS transistor are connected in common to form an input and output, respectively, and the source of the second N-channel MIS transistor is connected to the source of the first P-channel MIS transistor, and the drain is connected in common. A gate of the first power source is connected to a connection point between the first resistor and the second resistor or to the first power source, and the second P-channel type MI
The source of the S transistor is the first N-channel MIS.
A semiconductor circuit characterized in that a source and a drain of a transistor are connected to the second power source, and a gate is connected to a connection point between the second resistor and the third resistor or to the second power source.
JP5827484U 1984-04-20 1984-04-20 semiconductor circuit Pending JPS60169933U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5827484U JPS60169933U (en) 1984-04-20 1984-04-20 semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5827484U JPS60169933U (en) 1984-04-20 1984-04-20 semiconductor circuit

Publications (1)

Publication Number Publication Date
JPS60169933U true JPS60169933U (en) 1985-11-11

Family

ID=30583621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5827484U Pending JPS60169933U (en) 1984-04-20 1984-04-20 semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS60169933U (en)

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