JPS60169961A - Control system of bus expansion adapter - Google Patents

Control system of bus expansion adapter

Info

Publication number
JPS60169961A
JPS60169961A JP2559984A JP2559984A JPS60169961A JP S60169961 A JPS60169961 A JP S60169961A JP 2559984 A JP2559984 A JP 2559984A JP 2559984 A JP2559984 A JP 2559984A JP S60169961 A JPS60169961 A JP S60169961A
Authority
JP
Japan
Prior art keywords
bus
data bus
data
input
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2559984A
Other languages
Japanese (ja)
Inventor
Yoshiaki Kageyama
蔭山　芳明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2559984A priority Critical patent/JPS60169961A/en
Publication of JPS60169961A publication Critical patent/JPS60169961A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To add simply a required I/O connecting a driving adaptor to the end part of a data bus to add an I/O, and controlling the connection/disconnection of a data bus only by a bus control signal from the added I/O side. CONSTITUTION:In case of adding a required I/O, the driving adaptor 11 is connected to the end part of the data bus 51 and the I/O12 to be added it connected to the driving adaptor 11 through data bus 61. An address to be accessed by the added I/O12 is inputted to an address decode circuit 13 to form a bus control signal and the signal is inputted to an enable terminal (EN) of the driving adaptor 11 to connect the input terminal of a normally disconnected data bus. When a CPU1 accesses the added I/O12, other I/Os are automatically turned off, the address is decoded by an address decoding circuit 13 and a bus control signal is sent to the driving adaptor 11. Thus, the data bus is connected and the data are transferred between the CPU1 and the I/O12.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明はデータ処理装置（ＯＰＵ）で制御され、所定数
の入出力装置（Ｉｌｏ）を接続しうるスロット数を有す
るデータバスに該スロット数を超える■１０を接続する
だめのバス拡張アダプタ制御方式％式％ （２）従来技術と問題点 従来、ＯＰＵのＩ１０バスには所定数のＩｌｏ　出入口
が決っておシこれをスロット数という。このスロット数
の制限はデータ転送用ドライバ（トランシーバ）の容量
と入出力端部の構造に依存する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a data bus that is controlled by a data processing unit (OPU) and has a number of slots to which a predetermined number of input/output devices (Ilo) can be connected. (2) Conventional technology and problems Conventionally, the I10 bus of an OPU has a predetermined number of Ilo entrances and exits, which is called the number of slots. This limit on the number of slots depends on the capacity of the data transfer driver (transceiver) and the structure of the input/output end.

従って、Ｉ１０スロット数を拡張したい場合、ドライバ
能力の増加は価格的に、も容積的にも国難であ？シ、又
、入出力端部の増設は物理的な制約にょシ簡単には実現
できない。Therefore, if we want to expand the number of I10 slots, is increasing the driver capacity a national problem in terms of price and volume? Furthermore, adding more input/output terminals cannot be easily realized due to physical constraints.

（３）発明の目的 本発明の目的は所定のスロット数を有するＯＰＵのデー
タバスに対して追加スロットを接続するためのバス拡張
アダプタ制御方式を提供することである。(3) Object of the Invention An object of the present invention is to provide a bus expansion adapter control method for connecting additional slots to the data bus of an OPU having a predetermined number of slots.

（４）発明の構成 前記目的を達成するため、本発明のバス拡張アダプタ制
御方式はデータ処理装置と複数の入出力装置とがバスを
介して接続されるとともに、該バスに拡張アダプタを介
して単一または複数の入出力装置が接続されるデータ飽
理システムであって、該拡張アダプタを介してパスに接
続される入出力装置へのアクセスを検出する検出部を設
け、該検出部の検出信号によシ前記拡張アダプタを接断
しデータ処理装置に対するデータの入出力を制御するよ
うにしたことを特徴とするものである。(4) Structure of the Invention In order to achieve the above object, the bus expansion adapter control system of the present invention connects a data processing device and a plurality of input/output devices via a bus, and connects a data processing device and a plurality of input/output devices to the bus via an expansion adapter. A data saturation system to which a single or multiple input/output devices are connected, comprising a detection unit that detects access to the input/output device connected to a path via the expansion adapter, and detecting the detection unit. The present invention is characterized in that input/output of data to and from the data processing device is controlled by connecting/disconnecting the expansion adapter in response to a signal.

（５）発明の実施例 第１図は本発明の実施例の概略説明図である。(5) Examples of the invention FIG. 1 is a schematic explanatory diagram of an embodiment of the present invention.

同図において、０ＰＵＩによシ制御されたデータバス４
にメモリ２が接続されて命令、データの格納。In the figure, data bus 4 controlled by 0PUI
Memory 2 is connected to the memory 2 for storing instructions and data.

転送が行なわれ、データバス４から分岐したデータバス
５に対しＩｌｏ　５１−５２等がいもづる式に接続され
る。このＩ１０スロット数は前述のとおシ一定数に制限
されているから、ＡＡ’よシ右側に対し拡張するため、
データバス５の端部に駆動アダプタ１１を設け、データ
バス６を介して追加のｌ１０１２を接続する。ここで駆
動アダプタ１１は追加Ｉ／。Transfer is performed, and the Ilo 51-52 etc. are connected in a sequential manner to the data bus 5 branched from the data bus 4. Since the number of I10 slots is limited to a certain number as mentioned above, in order to expand from AA' to the right side,
A drive adapter 11 is provided at the end of the data bus 5 and an additional l1012 is connected via the data bus 6. Here, the drive adapter 11 is an additional I/.

１２に対する入出力データを双方向に切換え転送駆動す
る機能を有する。It has a function of bidirectionally switching and transferring input/output data to and from 12.

第２図は第１図の要部の詳細説明図である。FIG. 2 is a detailed explanatory diagram of the main part of FIG. 1.

同図において、複数ＶＯＳ１＊　３２等に対し入出力す
るデータはＯＰＵ　１に含まれるドライバによシ、デー
タバス５１を介しデータを、アドレスバス５２を介しア
ドレスを転送する。この場合、たとえばアドレスバス５
２を介しＩｌｏ　５１がアクセスされ、データバス５１
を介しデータをｏｐｔｙｉに送るが、この場合他のＩｌ
ｏ　３ｇの入出力はオフ（ハイインピーダンス）に制御
される。このように、ドライバ容量によシ制限されるス
ロット数のｉｌｏのうち、アクセスｉ１０のみがオン（
ローインピーダンス）となシ、他のＩｌｏはオフ（ハイ
インピーダンス）に制御される。しかし、前述のように
、制限されたスロット数を超えたス胃ットに対しては、
ドライバの容量が不足する。そこで既存のｉｌｏには影
響を与えることなく、所要のｉｌｏを追加するため、本
発明ではデータバス５１の端部に駆動アダプタ１１を設
け、データバス６１を介してこれに追加ｌ１０１２を接
続する。駆動アダプタ１１はパスの接断可能で双方向の
方向制御ができるドライバ、すなわちトランクーパであ
る。このパスの接断と方向制御はＣＰＵ　１では制御さ
れないから、追加されたＩ／１２にアクセスされるアド
レスをアドレスデコード回路１３に入れパス制御信号を
作シ、該信号を駆動アダプタ１１のイネーブル端子（Ｂ
Ｎ）に入れ、常時断のデータバスの入力端を接とする。In the figure, data to be input/output to and from a plurality of VOS 1* 32 etc. is transferred to a driver included in OPU 1 via a data bus 51 and an address via an address bus 52. In this case, for example, address bus 5
Ilo 51 is accessed via data bus 51
, but in this case other Il
o 3g input/output is controlled off (high impedance). In this way, among the ilo slots whose number is limited by the driver capacity, only access i10 is on (
(low impedance), the other Ilo is controlled to be off (high impedance). However, as mentioned above, for slots exceeding the limited number of slots,
Driver capacity is insufficient. Therefore, in order to add the required ILO without affecting the existing ILO, in the present invention, the drive adapter 11 is provided at the end of the data bus 51, and the additional ILO is connected to it via the data bus 61. The drive adapter 11 is a driver that can connect/disconnect paths and control bidirectional direction, that is, a trunker. Since the connection/disconnection and direction control of this path are not controlled by the CPU 1, the address to be accessed by the added I/12 is input into the address decoding circuit 13 to generate a path control signal, and this signal is sent to the enable terminal of the drive adapter 11. (B
N) and connect it to the input end of the normally disconnected data bus.

一方、０ＰＵ１ではハードウェアに追加的を組入れるだ
けでよい。従ってＯＰＵ　１から追加ｌ１０１２をアク
セスすると、他のｉｌｏは自動的にオフ（ハイインピー
ダンス）とされ、このアドレスがアドレスデコード回路
１５で解読されてバス制御信号が駆動アダプタ１１に送
られ、データバスを接としデータはＯＰＵ　１とｌ１０
１２間で転送される。このように制御はｌ１０１２側か
らの制御信号のみによシ行なわれる。On the other hand, with 0PU1, only additional hardware needs to be incorporated. Therefore, when the additional ILO 1012 is accessed from OPU 1, the other ILOs are automatically turned off (high impedance), this address is decoded by the address decoding circuit 15, a bus control signal is sent to the drive adapter 11, and the data bus is Contact data is OPU 1 and l10
It is transferred between 12 and 12. In this way, control is performed only by control signals from the l1012 side.

（６）発明の詳細 な説明したように、本発明によれば、ス筒ット数の限定
されたデータバスにＩｌｏを追加するには、データバス
の端部に駆動アダプタを設けて行ない、追加Ｉ１０側か
らのバス制御信号のみによシデータバスの接断を制御す
るものである。これによシ、既存のＣＰＵの工んおよび
Ｉんドライバ等に何ら影響を与えることなく、所要のＩ
ｌｏを簡単に追加することが可能となる。(6) As described in detail, according to the present invention, in order to add Ilo to a data bus with a limited number of slots, a drive adapter is provided at the end of the data bus, The connection/disconnection of the data bus is controlled only by the bus control signal from the additional I10 side. This allows you to install the required I/O without affecting existing CPU architecture or I/O drivers, etc.
It becomes possible to easily add lo.

【図面の簡単な説明】[Brief explanation of drawings]

８１図は本発明の概略説明図、第２図は第１図の詳細説
明図であシ、図中、１はＣＰＵ、　２はメモリ、３ｉｖ
５２ｉ２はＩｌｏ　ｓ　４１５．５ｔ　ｅ　６ｅ　６１
ｅはデータバス、５２＊６２はアドレスバス、１１は駆
動アダプタ、１３はアドレスデコード回路を示す。 特許出願人富士通株式会社 復代理人弁理士　１）坂　善　重81 is a schematic explanatory diagram of the present invention, and FIG. 2 is a detailed explanatory diagram of FIG. 1. In the figure, 1 is a CPU, 2 is a memory, and 3iv
52i2 is Ilo s 415.5t e 6e 61
Reference numeral e indicates a data bus, 52*62 an address bus, 11 a drive adapter, and 13 an address decoding circuit. Patent applicant: Fujitsu Limited, sub-agent patent attorney 1) Yoshishige Saka

Claims (1)

【特許請求の範囲】[Claims] データ処理装置と複数の入出力装置とがバスを介して接
続されるとともに、該バスに拡張アダプタを介して単一
または複数の入出力装置が接続されるデータ処理システ
ムであって、該拡張アダプタを介してバスに接続される
入出力装置へのアクセスを検出する検出部を設け、該検
出部の検出信号によシ前記拡張アダプタを接断しデータ
処理装置に対するデータの入出力を制御するようにした
ことを特徴とするバス拡張アダプタ制御方式。A data processing system in which a data processing device and a plurality of input/output devices are connected via a bus, and a single or a plurality of input/output devices are connected to the bus via an expansion adapter, wherein the expansion adapter A detection unit is provided to detect access to an input/output device connected to the bus via the bus, and the expansion adapter is connected or disconnected according to a detection signal from the detection unit to control data input/output to the data processing device. A bus expansion adapter control method characterized by:
JP2559984A 1984-02-14 1984-02-14 Control system of bus expansion adapter Pending JPS60169961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2559984A JPS60169961A (en) 1984-02-14 1984-02-14 Control system of bus expansion adapter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2559984A JPS60169961A (en) 1984-02-14 1984-02-14 Control system of bus expansion adapter

Publications (1)

Publication Number Publication Date
JPS60169961A true JPS60169961A (en) 1985-09-03

Family

ID=12170367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2559984A Pending JPS60169961A (en) 1984-02-14 1984-02-14 Control system of bus expansion adapter

Country Status (1)

Country Link
JP (1) JPS60169961A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6284845U (en) * 1985-11-13 1987-05-30
JPS63220385A (en) * 1987-03-09 1988-09-13 Nec Corp Terminal equipment for card
JPS6478350A (en) * 1987-09-19 1989-03-23 Pfu Ltd Access control system
JPH0325949U (en) * 1989-07-25 1991-03-18

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58203537A (en) * 1982-05-22 1983-11-28 Nissin Electric Co Ltd Controlling method of bus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58203537A (en) * 1982-05-22 1983-11-28 Nissin Electric Co Ltd Controlling method of bus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6284845U (en) * 1985-11-13 1987-05-30
JPS63220385A (en) * 1987-03-09 1988-09-13 Nec Corp Terminal equipment for card
JPS6478350A (en) * 1987-09-19 1989-03-23 Pfu Ltd Access control system
JPH0325949U (en) * 1989-07-25 1991-03-18

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