JPS60180134U - cyclic filter device - Google Patents

cyclic filter device

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Publication number
JPS60180134U
JPS60180134U JP15416584U JP15416584U JPS60180134U JP S60180134 U JPS60180134 U JP S60180134U JP 15416584 U JP15416584 U JP 15416584U JP 15416584 U JP15416584 U JP 15416584U JP S60180134 U JPS60180134 U JP S60180134U
Authority
JP
Japan
Prior art keywords
circuit
weighting
filter device
charge transfer
simultaneously applied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15416584U
Other languages
Japanese (ja)
Other versions
JPS6312588Y2 (en
Inventor
義博 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15416584U priority Critical patent/JPS60180134U/en
Publication of JPS60180134U publication Critical patent/JPS60180134U/en
Application granted granted Critical
Publication of JPS6312588Y2 publication Critical patent/JPS6312588Y2/ja
Granted legal-status Critical Current

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  • Filters That Use Time-Delay Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の巡回型フィルタ装置の回路構成を示すブ
遁ツク図、第2図は本考案の基本的実施例の等価回路を
示すブロック図、第3図は本考案の他の一実施例の等価
回路を示すブロック図、第4図は本考案のさらに他の一
実施例の等価回路を示すブロック図、第5図は第4図の
回路を集積化した一実施例の電荷堰および電極の形状を
示す要部上面図、第6図は同じく第4図の回路を集積化
した別の実施例を示す要部上面図、第7図は本考案のさ
らに異なる実施例の等価回路を示すブロック図、第8図
は前回に示した実施例の周波数特性を示す線図、第9図
は重み係数補正用チャンネルを有する実施例の要部上面
図である。 1:入力端子、2:第1加算回路、3および4:遅延回
路、5〜9:重み付は回路、10:第2加算回路、21
 : CTD、22:入力端子、23〜27:重み付は
回路、28:出力端子、29:第2CTD、 31〜3
5:重み係数付与用チャンネル、36:電荷堰、S□〜
S5:ソース領域、R□およびR2ニドレイン領域、7
0:増幅器、94:補正用チャンネル、SaおよびSb
:ソース領域。   ゛ 補正 昭59.11.9 考案の名称を次のように補正する。 ■考案の名称  巡回型フィルタ装置 実用新案登録請求の範囲、図面の簡単な説明を次のよう
に補正する。 O実用新案登録請求の範囲 2系統の電荷転送素子と、入力信号が印加される入力端
子と、濾波ずみの出力信号を取り出す出力端子と、前記
2系統の電荷転送素子の一方の所定ビットに電荷的に結
合される正の重み付は回路群と、他方の電荷転送素子に
設けられた負の重み付は回路群とを備え、前記正負の重
み付は回路群の一部には入力信号が同時に印加され、残
りの回路群には出力信号が同時に印加されるよう構成さ
れた巡回型フィルタ装置において、 前記2系統の電荷転送素子は電荷堰により定められた蛇
行状の電荷転送路を有するとともに平行に隣接配置され
、かつ2系統の電荷転送素子の各ビットは信号電荷が混
合されて転送されるよう互いに連通して構成され、かつ
前記重み付は回路は−第1および第72電極からなる2
重ゲート構造を有し、前記入力信号および出力信号が正
の重み付は回路群のそれぞれ第1電極と、負の重み付は
回路群のそれぞれ第2電極とに同時に印加されるように
構成したことを特徴とする巡回型フィルタ装置。 図面の簡単な説明 第1図は従来の巡回型フィルタ装置の回路構成を示すブ
ロック図、第2図は従来の基本的等価回路を示すブロッ
ク図、第3図は第1の従来例の等価回路を示すブロック
図、第4図は第2の従来例の等価回路を示すブロック図
、第5図は第4図の回路を集積化した電荷堰および電極
の形状を示す要部上面図、第6図は本考案の一実施例を
示す要部上面図、第7図は第6図の正係数チャネルと負
係数チャネルにおける電位分布図、第8図は本考案のロ
ーパスフィルタの直流特性図、第9図は第5図に示した
従来のローパスフィルタの直流特性図である。 1:入力端子、2:第1加算回路、3および4:遅延回
路、5〜9:重み付は回路、10:第2加算回路、21
 :CTD、 22 :入力端子、23〜27:重み付
は回路、28:出力端子、29:第2CTD、 31〜
35:重み係数付与用チャンネル、36:電荷堰、Si
−S5:ソース領域、R1およびR2ニドレイン領域、
φ1.φ2 :転送電極。 22八−十二一二 34  ″″ しC T″S2
Fig. 1 is a block diagram showing the circuit configuration of a conventional recursive filter device, Fig. 2 is a block diagram showing an equivalent circuit of a basic embodiment of the present invention, and Fig. 3 is another embodiment of the present invention. FIG. 4 is a block diagram showing an equivalent circuit of still another embodiment of the present invention. FIG. 5 is a block diagram showing an equivalent circuit of another embodiment of the present invention, and FIG. FIG. 6 is a top view of the main part showing the shape of the electrode, FIG. 6 is a top view of the main part showing another embodiment in which the circuit of FIG. 4 is integrated, and FIG. 7 is an equivalent circuit of still another embodiment of the present invention. FIG. 8 is a diagram showing the frequency characteristics of the embodiment shown last time, and FIG. 9 is a top view of the main part of the embodiment having a weighting coefficient correction channel. 1: Input terminal, 2: First addition circuit, 3 and 4: Delay circuit, 5 to 9: Weighting circuit, 10: Second addition circuit, 21
: CTD, 22: Input terminal, 23 to 27: Weighted circuit, 28: Output terminal, 29: Second CTD, 31 to 3
5: Channel for weighting coefficient, 36: Charge weir, S□~
S5: Source region, R□ and R2 Ni dorain region, 7
0: Amplifier, 94: Correction channel, Sa and Sb
: Source area.゛Amendment November 9, 1982 The name of the invention is amended as follows. ■Name of the invention The scope of the utility model registration claims for the cyclic filter device and the brief description of the drawings are amended as follows. O Utility Model Registration Claims Two systems of charge transfer devices, an input terminal to which an input signal is applied, an output terminal from which a filtered output signal is taken out, and a charge transfer device in a predetermined bit of one of the two systems. The positive weighting provided on the other charge transfer element includes a circuit group, and the positive weighting provided on the other charge transfer element includes a circuit group. In the recursive filter device configured such that output signals are simultaneously applied and the output signals are simultaneously applied to the remaining circuit group, the two systems of charge transfer elements have meandering charge transfer paths defined by charge weirs, and The bits of the two systems of charge transfer elements are arranged in parallel and adjacent to each other and are configured to communicate with each other so that signal charges are mixed and transferred, and the weighting circuit is composed of -first and 72nd electrodes. 2
It has a heavy gate structure, and the input signal and the output signal are configured such that positive weighting is simultaneously applied to each first electrode of the circuit group, and negative weighting is simultaneously applied to each second electrode of the circuit group. A recursive filter device characterized by: Brief Description of the Drawings Fig. 1 is a block diagram showing the circuit configuration of a conventional recursive filter device, Fig. 2 is a block diagram showing a conventional basic equivalent circuit, and Fig. 3 is an equivalent circuit of the first conventional example. FIG. 4 is a block diagram showing an equivalent circuit of the second conventional example, FIG. The figure is a top view of essential parts showing an embodiment of the present invention, FIG. 7 is a potential distribution diagram in the positive coefficient channel and negative coefficient channel of FIG. 6, FIG. 8 is a DC characteristic diagram of the low-pass filter of the present invention, and FIG. FIG. 9 is a DC characteristic diagram of the conventional low-pass filter shown in FIG. 1: Input terminal, 2: First addition circuit, 3 and 4: Delay circuit, 5 to 9: Weighting circuit, 10: Second addition circuit, 21
:CTD, 22: Input terminal, 23-27: Weighting circuit, 28: Output terminal, 29: Second CTD, 31-
35: Weighting coefficient imparting channel, 36: Charge weir, Si
- S5: source region, R1 and R2 Ni dorain region,
φ1. φ2: Transfer electrode. 228-121234 ″″ しCT″S2

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 遅延用電荷転送素子と、入力信号を印加される入力端子
と、ろ波ずみの信号を取り出す出力端子と、それぞれ上
記電荷転送素子の所定ビットに電荷的に結合される重み
付は回路群と番具え、上記重み付は回路群の一部には入
力信号が同時に印加され、該重み付は回路群中の残りの
ものには出力端子に現れる信号が同時に印加されること
′を特徴とする巡回型フィルタ装置。
The delay charge transfer element, the input terminal to which the input signal is applied, the output terminal to take out the filtered signal, and the weighting that is electrically coupled to a predetermined bit of the charge transfer element are determined by the circuit group and number. The weighting is a cyclic method characterized in that the input signal is simultaneously applied to some of the circuit groups, and the signal appearing at the output terminal is simultaneously applied to the remaining circuit groups. Type filter device.
JP15416584U 1984-10-11 1984-10-11 cyclic filter device Granted JPS60180134U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15416584U JPS60180134U (en) 1984-10-11 1984-10-11 cyclic filter device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15416584U JPS60180134U (en) 1984-10-11 1984-10-11 cyclic filter device

Publications (2)

Publication Number Publication Date
JPS60180134U true JPS60180134U (en) 1985-11-29
JPS6312588Y2 JPS6312588Y2 (en) 1988-04-11

Family

ID=30712159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15416584U Granted JPS60180134U (en) 1984-10-11 1984-10-11 cyclic filter device

Country Status (1)

Country Link
JP (1) JPS60180134U (en)

Also Published As

Publication number Publication date
JPS6312588Y2 (en) 1988-04-11

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