JPH0457368A - A/d converter - Google Patents

Abstract

PURPOSE:To mutually offset the asymmetry of currents for actuarizing the efficient layout by a method wherein a MOSFET is composed of a pair of MOSFETs in the mutually inverse source/drain directions. CONSTITUTION:A pair of gates 55a, 55b are formed in the first and second applicable MOS.FETs 50A, 50B parallel-connected and then the first - third ion-implanted regions 51-53 are formed as if holding the pair of gates 55a, 55b. Next, the second ion-implanted regions 52a, 52b located in the central positions are respectively common-connected to be the source regions and the drain regions while all the first and third ion-implanted regions 51, 53 are common-connected to be drain regions or the source regions. Through these procedures, within said MOS.FETs 50A, 50B, even if the source and drain are replaced with each other, the overlapping capacitors and the source/ drain currents will be kept unchanged, thereby enabling the offset amount in all the comparators to be equalized.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention uses MOS/FET as a comparator element.
A/D using (MOS type field effect transistor)
Regarding converters.

"Prior Art" A MOS-FET is used as a comparator element constituting a comparator for an A/D converter.

As is well known, the MOS-FET has a configuration as shown in FIG.

In figures A and B, S is the source (source region), D is the lower drain (drain region), and G is the gate (gate region).
It is. Reference numerals 20, 21, and 22 are extraction electrodes for each area, and 24 and 25 are contact areas thereof. 2
6 is a semiconductor substrate.

As is well known, a general feature of a MOS-FET is that the source and drain are interchangeable. As is clear from Figure 5, this is true for the source S and drain D.
This is because they have the same structure.

By the way, in the actual manufacturing process of MOS-FET, in the ion implantation process to form the source and drain, a certain angle θ (for example, 7°) is applied as shown in FIG.
It is common practice to inject with

At this time, as shown in the figure, the amount of overlap between the source/drain region and the gate differs between the A side and the B side.

In the case of the figure, the amount of overlap with the region is greater on the B side.

Therefore, the value of the saturation current of the transistor differs depending on whether the A or B side is used as the drain D. As a result, if the source and drain are swapped, strictly speaking, the symmetry of the characteristics does not hold.

Further, the overlap capacitance between the source S (or drain D) and gate G as a parasitic capacitance of the MOS-FET is also different between the A side and 842g.

Now, consider a case where such a transistor is applied to a chopper type comparator as shown in FIG.

In the chopper type comparator shown in the figure, Vref
is the reference voltage, Vin is the input voltage, T, U, and X are the transfer gates, and C is the coupling capacitance (charging/discharging capacitor)
, Y is an inverter.

Each of the transfer gates T, U, and X is configured by a pair of MOS-FETs of different conductivity types connected in parallel.

In this chopper type comparator, when the clock φ is at high level, the reference voltage V ref is applied to the coupling capacitance C.
The difference between the logical threshold level Vth of the inverter Y and the logical threshold level Vth of the inverter Y is stored. Next, when the clock φ becomes low level, the input voltage Vin is applied to the input of the coupling capacitor C, so that the input terminal Z of the inverter Y has a change from the logic threshold level vth by the difference between V ref and Vin. Vert and Vi
The comparison result of n appears at the output of inverter Y.

The problem at this time is that when the transfer gate X is turned off, an offset voltage is generated at the input terminal Z of the inverter due to clock field through.

Factors that cause this field-through include gate capacitance and gate-source (or gate-drain) overlap capacitance.

This is because when the transfer gate X turns off, the change in the values of these capacitances causes current to flow from the gate or source, causing an offset.

[Problems to be Solved by the Invention] By the way, A/D converters, especially parallel A/D converters, use a large number of comparators.If all the comparators could be laid out in the same direction, There is no difference in the amount of offset, and the linearity as an A/D converter is very good.

However, when considering an efficient layout, it is not a good idea to arrange them all in the same direction, and usually the parallel type A
In the case of a /D converter, a large number of comparators are arranged in a series as shown in FIG.

Figure 8 shows an example of a 4-bit configuration, where C8 to C15 are comparators, and the resistor RO-C15 is connected to the input stage.
R17 is a resistor for obtaining a standard reference voltage. Comparators C0-Cl3 have analog signals (input voltage V
in) is commonly input.

Do-D15 is a latch circuit, 3 is an encoder,
A 4-bit digital signal is output from this.

When using a 4-bit configuration, for efficient layout, it is necessary to use comparators (for example, in units of 8 as shown in the figure).
It is better to arrange CO-C7) and (C8 to C15) in parallel.

Therefore, in such an A/D converter, a large number of comparators are often arranged in a series. Therefore, since the direction of the comparator is reversed depending on the column, the MOS-
FET and comparators C8 to C15 placed on the right side
The source/drain direction is opposite to that of the MOS-FET.

On the other hand, in this arrangement, when these comparators Co-Cl3 are formed on the semiconductor substrate 26 at the same time, the ion implantation directions into the semiconductor substrate 26 are the same.

Therefore, for the reasons mentioned above, if the direction of the source and drain changes depending on the comparator, the overlap capacitance and the value of the source and drain current will differ, resulting in a difference in the amount of offset between the left side and the right side, making it difficult to accurately This becomes an obstacle when performing an A/D conversion operation.

As described above, the currently widely used ion implantation technique with an angle deteriorates the symmetry of the characteristics of MOS-FETs, resulting in differences in characteristics such as overlap capacitance and saturation current.

Furthermore, for the same reason, the gain of the inverter Y also differs, which poses a problem.

In order to avoid these problems, it is necessary to align the source and drain directions of the individual MOS-FETs in the inverters and transfer gates of all comparators.

However, this imposes restrictions on the layout and increases the chip area, so it cannot be said to be a very good measure.

Therefore, the present invention provides an A/D converter that is less affected by the directionality of the MOS-FET.

"Means for Solving the Problems" In order to solve the above-mentioned problems, in the present invention, in a converter for a parallel type A/D converter, as a MOS/FET for a transfer gate used in the converter, a transistor connected in parallel is used. A pair of gates is formed in each of the first and second MOS-FETs, and first to third ion implantations are performed to sandwich the pair of gates. The second ion-implanted regions located in the center are connected in common to form a source region or a drain region, and the first and third ion-implanted regions are all connected in common to form a drain region. Alternatively, it is characterized by being made into a source region.

"Function" As shown in Figures 1 and 2, the MOS-FET 5 has source and drain channel directions opposite to each other.
In 0A and 50B, one source and the other drain are formed in a common region, and this is used as a source (or drain) electrode.

Further, the remaining source and drain are connected to each other by a wiring layer to form a drain (or source) electrode. Further, their gates are connected as one, and this is used as a gate electrode to form - MOS-FETs.

Then, this MOS-FET has source and drain directions that are opposite to each other, and the overlap between the gate and source is small and large, and even if the directions are switched, the total amount of overlap does not change. do not have.

The same applies to the overlap between the gate and drain.

As a result, in this MOS-FET, even if the source and drain are interchanged, there is no change in the overlap capacitance or the source-drain current, and the offset amount is equal in all comparators.

"Example" Next, an example of the A/D converter according to the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

FIG. 1 shows an embodiment in which the present invention is applied to transfer gates T, U, and X of a chopper type comparator as shown in FIG.

The basic configuration of FIG. 1 is the configuration shown in FIG. 2.

Therefore, for convenience of explanation, the explanation will be made with reference to FIG. 2 as well.

First, as shown in FIG. 1, first and second MOS-FETs 50A and 50B connected in parallel are used.

These first and second MOS-FETs 50A.

In 50B, as shown in FIGS. 2A and 2B, a gate G is formed, and first to third ion implantation regions 51, 52, and 53 are formed so as to sandwich this gate G.

The second ion implantation region 52 located at the center is connected in common to serve as a source region (or drain region) as shown in FIG. 1, and the first and third ion implantation regions 51 . 53 are commonly connected to form a drain region (or source region).

If three ion implantation regions 51 to 53 are formed sandwiching the gate G as shown in FIG. 2B, in other words, FIG.
If the gate, source, and drain regions are formed to have opposite source and drain directions as shown by the solid arrows, the following characteristics can be obtained.

That is, if such a configuration is adopted and corresponding regions are formed by ion implantation from the same direction at an angle θ as shown in FIG. 2B, the overlap between the gate and source and the gate
In either case, you will have a small overlap and a large overlap between the drains.

As shown in FIGS. 3A and 3B, even if the directions of the source and drain are switched, the total amount of overlap remains unchanged and is the same as in FIGS. 2A and B.

As a result, even if the source and drain are swapped,
The amount of overlap and source/drain current of the MOS-FETs do not change.

In FIG. 2, 55a is a gate electrode, 56a is a common source electrode, and 57 to 59 are contact regions.

Further, in FIG. 1, Z is an input terminal, and Cout is a comparison output. and 51a to 53a and 51b to 53b
is an ion implantation region, which functions as a source S or a drain D.

55 and 56 are common electrodes for the source S or drain D.

The operation of the configuration in FIG. 1 is similar to that in FIG. 7, and to explain the case where it is applied to the transfer gate
A voltage difference between f and the threshold voltage yth of the inverter Y is accumulated in the coupling capacitor C.

Then, when the clock φ becomes a low level, the input voltage Vin is applied to the input of the coupling capacitor C, so the output terminal Z of the coupling capacitor C has a voltage V by the difference between Vref and ■in.
Changes from th. This is inverted and amplified and the comparison output Co
It is used as ut.

At this time, an offset is generated in the potential of 2 due to the clock field through of the transfer gate x.

However, if configured as shown in Figure 1, the overlap capacitance and drain current will be the same in each column even if the source and drain directions are reversed in the arrangement as shown in Figure 8.
The offset voltages generated in the comparators CO to C7 on the left side of the diagram are equal to the offset voltages generated in the comparators 08 to C15 on the right side.

Therefore, the A/D conversion characteristics (linearity) on the left and right sides match, and the conversion characteristics are improved.

Note that when an A/D converter is configured with a large number of comparators, the number of arrays may be three or more.

Similarly, in the inverter Y shown in FIG. 7, when arranged as shown in FIG. 8, the directions of the source and drain are reversed. If the directions are reversed, the values of the source-drain currents will change, resulting in different gains for the left and right inverters.

This difference in gain also affects the linearity error of the A/D converter.

Therefore, if this inverter Y is configured as shown in FIG. 4 using two MOS-FETs having the configuration shown in FIG. 2, there will be no difference in gain.

In the figure, 56a + 56b are source electrodes,
FIG. 8 is a block diagram of a parallel type A/D converter, in which 60 has a common gate electrode and 61 has a common gate electrode.

It is a rain electrode.

"Effects of the Invention" As explained above, according to the present invention, by configuring MOS-FETs having mutually opposite source and drain directions as one 03-FET, the source and drain caused by the manufacturing process The overlapping capacitance in the drain direction and the asymmetry of the source-drain current can be canceled out.

This reduces directional constraints in the layout of MOS-FETs, making it possible to realize an efficient layout.

50A, 50B ・ ・ MOS-FET51 a
~53a, 5lb~53b... Ion implantation regions 55a, 55b, 56, 56a 56b, 60.61... Electrode

Claims (2)

[Claims] (1) In a parallel type A/D converter converter, first and second MOS/FETs connected in parallel are used as transfer gate MOS/FETs used in this converter, and these first and second MOS/FETs are used. In addition to each MOS/FET having a pair of gates formed therein, first to third ion implantation regions are formed to sandwich these pair of gates, and a second ion implantation region located in the center is common to each of the MOS/FETs. An A/D converter characterized in that the first and third ion-implanted regions are connected together to form a source region or a drain region, and the first and third ion-implanted regions are all commonly connected to form a drain region or a source region. (2) In claim 1, the plurality of comparators are arranged in a plurality of rows, and the ion implantation directions of the first to third ion implantation regions are selected to be the same in each row. Characteristic A/
D converter.