JPS60182196A - Method of producing multilayer board - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a multilayer substrate, and particularly to the formation of an interlayer insulating film.

[Prior art]

Conventionally, when manufacturing multilayer substrates for hybrid integrated circuits made of thick or thin films, through-holes for interlayer connections are formed on conductor patterns formed by a normal thick-film or thin-film process including a 7-layer etching process. The process used was to form an interlayer insulating film and then form a conductor pattern, except for the parts where .

By the way, in forming this glabellar insulating film, a thick film method has been used in most cases because it is easy to manufacture without including any etching process, and the manufacturing cost is low.

However, since the interlayer insulating film #1 is coated on the entire surface except for the through-hole portion, the material cost is a large factor.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a multilayer substrate with low manufacturing cost.

[Structure of the invention]

In order to achieve the above object, the present invention aims to form an interlayer insulating film having almost the same pattern shape as the underlying conductor pattern except for the portions that will become through holes, thereby omitting the formation in unnecessary parts. be.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, as shown in FIG. 1, gold is coated on the entire surface of an insulating ceramic substrate 1 by screen printing, followed by drying and firing to form a gold layer 2.

Next, the gold layer 2 is formed into a desired pattern shape by photolithography, as shown in FIG.

On the first gold pattern 3 formed in this way, a screen having a slightly larger /4' turn that is approximately the same shape as the gold pattern 3 is used, and by a screen printing method,
An insulating layer containing aluminum oxide as a main component is formed, and through a drying and baking process, an interlayer insulating film 4 is formed as shown in FIG. 3.

Further, similarly to the first gold pattern, printing,
After firing and a photolithography process, a second gold pattern 5 is formed as shown in FIG.

The multilayer substrate formed in this manner requires only a small amount of insulating paste for forming an interlayer insulating film, and the manufacturing cost is low.

In addition, in the above embodiment, in order to improve the pattern accuracy when forming the conductor pattern,
Although the photolithography method was used, the i9 turn formation may be performed during printing by using a screen carrying a desired pattern. In this case, the same screen is used to form the interlayer insulating film, and an insulating paste with a slightly lower viscosity is used to intentionally create a lump, which eliminates the need to prepare a special screen and reduces costs. It is effective for In this case, if a through hole is required, the glabellar insulating film may be subjected to an IJ process.

In addition to reducing costs, the method of the present invention is also effective in preventing the occurrence of short circuits due to increased density of wiring patterns. As an example, an example of a long reading element is shown below.

The drive circuit for the long-length 9-element salt is usually composed of a hybrid integrated circuit (hybrid IC), which has a large number of integrated circuit (IC) chips mounted on a ceramic substrate.
As a result of the increased number of bits required for increased resolution, circuits have also become more complex. For example, in recent years,
Devices that require as many as 150 bonding points for one mounted IC chip are now being used. In this case, 150 bonding pads are formed around one Gui bonding node, and bonding is performed on each bonding pad, but the wiring layer has a line width of 50 μm and a line spacing of 5
Due to the high density of about 0 to 70 μm, shorts occur in about 10 places on one IC chip due to shorts between lines or shorts due to protrusion of the crimp wire during bonding. This is a cause that hinders the improvement of reliability.

Therefore, for example, Fig. 5 is an enlarged view of the main part, and Fig. 6 is an enlarged view of the main part.
As shown in the AA cross-sectional view of the figure, the first y+/nding node 12, the second y+/nding node 12, the second y+/nding pad 13, and the third
14, a fourth binding pad 15, a fifth pumping pad 16, and a first line 17, a second line 18, and a second line connected to these bonding pads 12 to 16, respectively. 3 line 19
, the fourth line 20, and the fifth line 2.1.
9 pumpings 12, 3rd pumping 9
The binding pad 14, the fifth binding pad 16 and the first line 17, the M3 line 19, the fifth line 21 and the binding/4' binding pad 11 are connected to the second binding pad 13, the fourth binding pad 15 and Prior to forming the second line 18 and the fourth line 20,
A ceramic substrate 1 is used as the first layer thick film conductor pattern.
The pattern is covered with an interlayer insulation layer V22 having approximately the same shape as the pattern. (This interlayer insulating film is also formed from a thick film pattern.) In addition, the second pumping layer, the fourth bonding node, the second line, and the fourth line are connected to the thick film of the second layer. It is formed as a conductive pattern.

By the way, the first layer conductor pattern, interlayer insulating film, and second layer conductor pattern are formed in the same process as the formation of other wiring layers on this hybrid board, which increases the number of man-hours. I can't stand it.

Also number 1. Third. A glabellar insulating film is formed on the fifth pumping unit 9rad so as to have a through hole 23 at the bonding portion.

In this way, when forming closely adjacent dending nodes and lines, every other conductor is formed as a first layer conductor/4' turn, and the top layer is separated from this one by #1. After covering with insulators and turns of the same shape, as the second conductor and turn, arrange the remaining Q bonding rod and line at the opening of the bonding pad and line. In addition to short circuits between adjacent lines, short circuits can occur even if the crimp wire protrudes from the bonding pad during wire bonding because the adjacent lines are covered with an interlayer insulating film. is almost completely eliminated, and the drive rotation, that is, the defective rate of hybrid ICs is significantly reduced.

For example, if the line width is 50 μm, the line spacing is 70 μm, and each pumping pad is 120 μm square, if all the lines and pumping pads are formed in the same layer as in the past, the wire will be bonded using a gold wire with a diameter of 25 μm. Although the short circuit occurrence rate during binding was -L°C-50, it can be improved by forming patterns of similar dimensions alternately as separate layers via an interlayer insulating film as described above. The short circuit occurrence rate during landing is O.

This structure is particularly effective in preventing short circuits due to ink sag or flow after printing when forming high-density /4 lines by the thick film method, but it is also effective in the thin film method. Needless to say.

〔Effect of the invention〕

As explained above, according to the present invention, when manufacturing a multilayer board, the interlayer insulating film is formed to have almost the same pattern shape as the underlying conductor layer, so it is not necessary to cover the entire surface as in the conventional method. Compared to the case of forming an interlayer insulating film, material costs can be significantly reduced, and manufacturing costs can be reduced.

[Brief explanation of the drawing]

Figures 1 to 4 are diagrams showing the manufacturing process of a multilayer board according to an embodiment of the present invention, and Figure 5 is a diagram showing the vicinity of the bonding pad when the method of the present invention is adopted in the drive circuit section of a long reading element. Figure 6 is an enlarged view of the main parts showing an example of the configuration of Figure 5.
-A sectional view. ■... Ceramic substrate, 2... Gold layer, 3... First gold layer, 4... Interlayer insulation film, 5... Second gold pattern, 11... Die number? Ending method, 1
2...1st Sondings (rad, 13...2nd
Ponding pad, 14...Third pounding pad, 15...Fourth H? Zondingturad, 1
6... Fifth bonding node, 17... First line, 18... Second line, 19... Third line, 2o... Fourth line, 21... Fifth line, 22
- Interlayer insulating film, 23... through hole. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] A method for manufacturing a multilayer board, which comprises forming an interlayer insulating film to have almost the same pattern shape as the underlying conductor layer, for manufacturing a multilayer board having two or more conductor layers. .