JPS60183761A - Thick film multilayer circuit substrate - Google Patents
Thick film multilayer circuit substrateInfo
- Publication number
- JPS60183761A JPS60183761A JP59038776A JP3877684A JPS60183761A JP S60183761 A JPS60183761 A JP S60183761A JP 59038776 A JP59038776 A JP 59038776A JP 3877684 A JP3877684 A JP 3877684A JP S60183761 A JPS60183761 A JP S60183761A
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- layer
- circuit
- insulating substrate
- circuit conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、テレビやビデオテープレコーダーなどに用い
ることのできる厚膜多層回路基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a thick film multilayer circuit board that can be used for televisions, video tape recorders, and the like.
（従来例の構成とその問題点）
近年、電子機器の軽薄短小化に対する要求はますます増
大し、そオんにともなって電子回路の高）１７度化が重
要な１ｉｌｌ１題となって来ている。電子回路の高密度
化は、それを構成する回路基板の高密度化、とりわけ多
層配線化が必要不可欠であり、昨今いろいろな多層配線
板が試みられている。(Conventional structure and its problems) In recent years, the demand for lighter, thinner, and smaller electronic devices has been increasing, and with this, increasing the height of electronic circuits to 17 degrees has become an important issue. There is. In order to increase the density of electronic circuits, it is essential to increase the density of circuit boards constituting the electronic circuits, especially multilayer wiring, and various multilayer wiring boards have recently been attempted.
ところで、多層回路基板として、セラミック絶縁基板上
にメタルグレーズ系のベーストを印刷、焼成して導体層
や抵抗体層を形成し、これらとガラスペース１−を組み
合わせて多層配線化したいわゆる厚膜多層回路基板がビ
デオテープレコーダーをはじめとして多くの電子機器に
採用されて来つつある。この厚膜釜Ｒり回路基板は、一
般に第１図に示す構成のものであり１図において、■は
セラミック絶縁基板、２ａ、２ｂ、２ｃ、２ｄは厚膜回
路導体層、３ａ 、 ３ｂはガラス系絶縁体層、４ａ
、 ４ｂはバイヤホールを通して各導体層間を接続した
部分、５は絶ね基板ｌに設けた貫通孔を通して基板両面
の名導体Ａ’ｌＪ間を接続したスルホール、６は厚膜抵
抗体ＪＰ）である。By the way, as a multilayer circuit board, a metal glaze base is printed and fired on a ceramic insulating substrate to form a conductor layer and a resistor layer, and these are combined with a glass space 1- to form a multilayer wiring, so-called thick film multilayer. Circuit boards are being used in many electronic devices including video tape recorders. This thick film circuit board generally has the configuration shown in Fig. 1. In Fig. 1, ■ is a ceramic insulating substrate, 2a, 2b, 2c, and 2d are thick film circuit conductor layers, and 3a and 3b are glass. system insulator layer, 4a
, 4b is a part connecting each conductor layer through a via hole, 5 is a through hole that connects the famous conductor A'lJ on both sides of the board through a through hole provided in the board l, and 6 is a thick film resistor JP). .
しかしこのように構成された／’Ｘ膜多層回路基板では
、厚膜抵抗体Ｒ４がガラス絶縁体層−１−に形成さｈで
いるために、以下のような不都合な点があった。However, the /'X film multilayer circuit board constructed in this way has the following disadvantages because the thick film resistor R4 is formed on the glass insulator layer -1-.
１） 抵抗体坑成時に、ガラス成分が抵抗体層に拡散し
抵抗−値の精度が低下する。1) When forming the resistor, glass components diffuse into the resistor layer, reducing the accuracy of the resistance value.
２）下層の１！！ｌ路ノリ体層の影響でガラス絶廊体層
の表面に凹凸か生し、その−１−に形成するジノ（抗体
Ｗｉの抵抗値イ’１７ ）’Ｕが、ｌ）るく、１代抗（
４（層の小面［、′ｊ化か図りにくい。2) Lower layer 1! ! Due to the influence of the l-road glue body layer, unevenness occurs on the surface of the glass barrier layer, and the resistance value of the antibody Wi (resistance value of the antibody Wi) 'U is 1) Anti(
4 (The small surface of the layer [, 'j is difficult to plan.
；）） 抵抗体層のレーザー１〜リミンクにＪｌいて、
ガラス絶縁体層を介しＣドＪ１・１に形成さ、Ｉシごい
る回ｙ８導体層に損（Ｍか生しやずく、’ｖ’（ｆ、
−Ｊ ”７ａ回路設計の白山度が小さくなる。;)) Laser 1 of the resistor layer ~ Jl in remink,
A loss (M) is formed on the C do J1.1 through the glass insulator layer,
-J "7a The whiteness of the circuit design becomes smaller.
（発明の目的）
本発明の目的は、ノブ膜抵抗体Ｒ’ｌの抵抗値精１庵に
すぐれたノブ膜多層回路Ｊ、ｌ； Ｉゾを提供すること
である。(Object of the Invention) An object of the present invention is to provide a knob film multilayer circuit J, l; I which is excellent in the resistance value of the knob film resistor R'l.
（発明の構成）
本発明は、セラミックＲ７（Ａ Ｍ＜ ｊＪｙ’板の一
方の３＝面上にＪ−ｆ膜回路導体層とＰｊ、 ｌｌＧ４
４層５抗体層とからなる抵抗回路を設け、他方の主面」
二に厚膜回路導体層とパイヤポールを設けたガラス絶縁
体Ｊｆ’ｌとを交互に積層し、ハイヤボールを通して回
路導体Ｊ’ｊ）ｌの層間を接続してなる多層回路を設け
、かつ、セラミック絶縁基板に設けた貫通孔を導通比し
て抵抗回路と多Ｒり回路とを電気的に接続したものであ
り、これにより高精度の抵抗体層を有する厚膜多Ｌ′り
回路基板が実現できるものである。(Structure of the Invention) The present invention includes a J-f film circuit conductor layer and Pj, llG4 on one 3= surface of the ceramic R7 (A M <jJy' plate
A resistance circuit consisting of 4 layers and 5 antibody layers is provided, and the other main surface is
Second, a multilayer circuit is provided by alternately laminating thick film circuit conductor layers and glass insulators Jf'l provided with wire poles, and connecting the layers of the circuit conductors J'j)l through higher balls, and A resistor circuit and a multi-R circuit are electrically connected by conducting through holes provided in an insulating substrate, thereby realizing a thick film multi-L' circuit board with a high-precision resistor layer. It is possible.
（実施１〈１の説明）
以下本発明の一実施例について、図面を参照しながら説
明する。(Explanation of Embodiment 1 <1) An embodiment of the present invention will be described below with reference to the drawings.
第２図は、本発明の一実施例における厚膜多層回路ノ、
（仮の断面を、示したものである。第２図において、７
はセラミックｊ′色縁基（反、８は基ｔＪｉ、に設けた
貫通孔を通して基板両面の各Ｊ４体層間を接続したスル
ホール、９ａ、 Ｏｂ、 ９ｃ、 ９ｄはそれぞれ各Ｊ
：ｊＬＪの厚膜回路心棒Ｒ’Ｊ、１０は厚膜Ｊｉｇ抗体
層、１１ａ。FIG. 2 shows a thick film multilayer circuit according to an embodiment of the present invention.
(This is a temporary cross section. In Figure 2, 7
8 is a through hole that connects each J4 body layer on both sides of the substrate through a through hole provided in the ceramic j' color edge base (respectively; 8 is a through hole provided in the base tJi; 9a, Ob, 9c, and 9d are each J
:jLJ thick film circuit mandrel R'J, 10 is thick film Jig antibody layer, 11a.
１１ｂは各層のガラス系絶縁体層、１２ａ、 １２ｂは
ガラス絶縁体層に設けたパイヤホールを通して各導体層
間を導通した部分である。Reference numeral 11b indicates a glass insulator layer of each layer, and 12a and 12b indicate electrical connection between each conductor layer through a wire hole provided in the glass insulator layer.
以−１−のように構成された本実施例の厚膜多層回路〕
＆板について以下その詳細を説明する。まず、アルミナ
などのセラミック絶縁基板７の一方の主面上に銀や銀−
パラジウムから成るメタルグレーズ系の厚膜回ｊ′８導
体層１」ａと、同一面−１−に酸化ルテニウムから成る
厚１侠抵抗体層１０をベーン、トの印刷、高温焼成によ
り形成する。セラミック絶縁基板７のもう一方の−ｉ：
、面には、銀や銀−パラジウムから成るメタルクレーズ
系のｔｌｉ ＋＋；ｐ回路導体層９１３．９Ｃ。Thick film multilayer circuit of this example configured as below-1-]
The details of & board will be explained below. First, on one main surface of the ceramic insulating substrate 7 made of alumina or the like,
A metal glaze-based thick conductor layer 1'a made of palladium and a thick resistor layer 10 made of ruthenium oxide are formed on the same surface by vane printing and high temperature firing. The other -i of the ceramic insulating substrate 7:
, and a metal craze-based tli++;p circuit conductor layer 913.9C made of silver or silver-palladium.
９ｄと、カラスを主成分とした絶縁体Ｊ：１１１ａ、
ｊｌｂを交互に積た１し、ガラス絶縁体層ｌｅａ、 ｌ
１１）に設けたパイヤポールを通して層間の回路導体層
９ｂ、 ９ｃ。9d, and insulator J:111a whose main component is crow.
1, glass insulator layers lea, l are stacked alternately.
11) between the circuit conductor layers 9b and 9c through the wire pole provided in the layer.
９ｄをそれぞれ相ノＪ：接続する導通部１２ａ、 １２
ｂを形成する。さらにセラミック絶縁基板７に設けた貫
通孔に／４４層を充填してスルホール８を形成し、厚膜
抵抗回路と各層の厚１瑛回路導体層とを電気的に接続す
る。Conductive parts 12a, 12 that connect 9d to phase J:
form b. Furthermore, the through holes provided in the ceramic insulating substrate 7 are filled with a /44 layer to form through holes 8, and the thick film resistor circuit and the 1-layer thick circuit conductor layer of each layer are electrically connected.
なお本実施例においては、Ｊｌ、−述したように回路導
体層敬で４層の多層回路基板を（１育成したが、本発明
ては回路導体層の層数は限定されるものではなく、任意
の層数を有する厚１１λ多層回路基板に適用できるもの
である。In this example, a four-layer multilayer circuit board (1) was grown with the circuit conductor layers as described above, but the number of circuit conductor layers is not limited in the present invention. It can be applied to a multilayer circuit board having an arbitrary number of layers and having a thickness of 11λ.
（発明の効果）
以」二の説明から明らかなように、本発明はセラミック
絶縁基板の一主面上に主として厚膜抵抗回路を形成し、
他方の主面」二に厚膜回路導体層とカラス絶縁体層とを
交互に積層して厚膜多層回路を形成した厚膜多層回路基
板であり、厚膜抵抗体層がＩド滑性に富んだセラミック
絶縁凸板上に直接形成されるため、抵抗値の精度が極め
てｉｌ’ｆｉ ＜、従ってＪｊＵ抗体の小面積化がはか
れるとともに、従来例のように抵抗体層へのガラス成分
の拡散が起らないため抵抗値が安定化し、かつ下層導体
Ｗ１の損傷もないことから回路設計の白山度が増大する
などのすぐれた効果を右するものである。(Effects of the Invention) As is clear from the following explanation, the present invention mainly forms a thick film resistance circuit on one main surface of a ceramic insulating substrate,
This is a thick film multilayer circuit board in which thick film circuit conductor layers and glass insulator layers are alternately laminated on the other main surface to form a thick film multilayer circuit. Since it is formed directly on a rich ceramic insulating convex plate, the accuracy of the resistance value is extremely high.Therefore, the area of the JjU antibody can be reduced, and unlike the conventional example, the glass component cannot be diffused into the resistor layer. Since this does not occur, the resistance value is stabilized, and since there is no damage to the lower conductor W1, excellent effects such as increased accuracy in circuit design are achieved.
第１図は、従来の厚膜多層回路基板の断面図、第２図は
、本発明の一実施例の厚膜多層回路基板の断面図である
。
７・・・セラミック絶縁基板、 ８ ・・・スルホール
、９ａ、 ９ｂ、 ９ｃ、 ９ｄ ”’厚膜回路導体層
、１０ ・・・厚膜抵抗体層、ｌｌａ、 ｌｌｂ・・・
ガラス絶縁体層、１２ａ、 １２ｂ・・パイヤホールを
通して回路導体層間を接続した導通部。
特許出願人 松下電器産業株式会社
第１図
？１３２図FIG. 1 is a sectional view of a conventional thick film multilayer circuit board, and FIG. 2 is a sectional view of a thick film multilayer circuit board according to an embodiment of the present invention. 7...Ceramic insulating substrate, 8...Through hole, 9a, 9b, 9c, 9d'' thick film circuit conductor layer, 10...Thick film resistor layer, lla, llb...
Glass insulator layers, 12a, 12b...conducting parts connecting circuit conductor layers through pie holes. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 1? Figure 132
Claims (1)
厚膜抵抗体層とからなる厚膜抵抗回路を設け、前記セラ
ミック絶縁基板の他方の主面」二に厚膜回路導体層とパ
イヤポールを右するガラス系絶縁体層とを交互に積層し
、前記バイヤホールを通して回路導体層の層間を接続し
てなる厚膜多ノ、り回路を設け、かつ、前記セラミック
絶ｕｉ ；Ｌ！＋板に設けられた貫通孔を通して前記厚
膜抵抗回路とＪｑ、 Ｍｔ多層回路とを電気的に接続し
てなることを特徴どする厚膜多層回路基板。A thick film resistance circuit consisting of a thick film circuit conductor layer and a thick film resistor layer is provided on one main surface of the ceramic insulating substrate, and a thick film circuit conductor layer and a pie pole are provided on the other main surface of the ceramic insulating substrate. A thick film multi-layer circuit is provided by alternately laminating glass-based insulating layers and connecting the circuit conductor layers through the via holes, and the ceramic insulating layer is laminated alternately. + A thick film multilayer circuit board, characterized in that the thick film resistance circuit and a Jq, Mt multilayer circuit are electrically connected through a through hole provided in a board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59038776A JPS60183761A (en) | 1984-03-02 | 1984-03-02 | Thick film multilayer circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59038776A JPS60183761A (en) | 1984-03-02 | 1984-03-02 | Thick film multilayer circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60183761A true JPS60183761A (en) | 1985-09-19 |
Family
ID=12534692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59038776A Pending JPS60183761A (en) | 1984-03-02 | 1984-03-02 | Thick film multilayer circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60183761A (en) |
-
1984
- 1984-03-02 JP JP59038776A patent/JPS60183761A/en active Pending
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