JPS60186020A - Etching method of ito - Google Patents

Etching method of ito

Info

Publication number
JPS60186020A
JPS60186020A JP59042511A JP4251184A JPS60186020A JP S60186020 A JPS60186020 A JP S60186020A JP 59042511 A JP59042511 A JP 59042511A JP 4251184 A JP4251184 A JP 4251184A JP S60186020 A JPS60186020 A JP S60186020A
Authority
JP
Japan
Prior art keywords
etching
aluminum
ito
substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59042511A
Other languages
Japanese (ja)
Inventor
Hirokazu Sakamoto
阪本 弘和
Takao Matsumoto
隆夫 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59042511A priority Critical patent/JPS60186020A/en
Publication of JPS60186020A publication Critical patent/JPS60186020A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices

Landscapes

  • Weting (AREA)

Abstract

PURPOSE:To form a fine pattern of an ITO by etching the ITO formed on the insulating layer of a substrate having electrode wirings made of aluminum or aluminum alloy with solution of specific temperature which contains specific amounts of sulfuric acid and ammonium sulfate. CONSTITUTION:Electrode wirings 3 made of aluminum or aluminum alloy are formed on an insulating substrate 20 as a circuit substrate 2, an interlayer insulator such as SiN and, in this case, an insulating film 4 is formed on the substrate 2, and a thin ITO film is then formed on the film 4. After this is patpterned by photoetching, it is etched, for example, with aqueous solution which contains 5-50wt% such as 10wt% of sulfuric acid and nitric acid with the liquid temperature at 50 deg.C or higher and lower than its boiling point such as 60 deg.C, thereby obtaining a patterned ITO1. In this case, even if defects 5, 6, 7 exist in the film 4, the ratio of the etching rates of the ITO and the aluminum or aluminum alloy is 15:1. Accordingly, the lower layer is not etched, and the wirings 3 made of the aluminum or aluminum alloy are not disconnected.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は工TOのエツチング方法、とくに工To(工
nainm Tin 0xide 、以下工TOと記す
。)のファインパターンを可能にするエツチング溶液に
関するものである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an etching method for etching TO, and in particular to an etching solution that enables a fine pattern of TO (nainm tin oxide, hereinafter referred to as TO). be.

〔従来技術〕[Prior art]

従来工Toをエツチングした後のデバイスはオ五図、第
2図、第8図、及び牙4図に示すようなものがあった。
Devices obtained after etching the conventional process were as shown in Figures 5, 2, 8, and 4.

第1図は従来の(aCZ)系エツチング溶液によって形
成された工To配線を示す部分千聞図、第2図はオ1図
A−A線に沿った断凹図、第8図riAA’又はAA’
糸台全台金なるfL極極線線含む回路基板に形成された
工TO全従来の塩酸系エツチング溶液でエツチングした
デバイスを示す部分平面因、牙4図はオ8図B−B線に
沿った断面図である。図中、(l)は工Toで成極配線
をなす。(2)は基板、(3jはAI!又はAI!系合
金よりなる′電極配線、(4)は層間絶縁膜、(51、
tel 、 fylは層間絶縁膜(4)にできる欠陥で
、(5)はピンホール欠陥、(6)は異物欠陥、(7)
は低密度欠陥である0銅は絶縁性基板である。
Fig. 1 is a partial cross-sectional view showing the wiring formed by a conventional (aCZ) based etching solution, Fig. 2 is a cutaway view taken along line A-A in Fig. 1, and Fig. 8 is a riAA' or AA'
A partial plane view showing a device etched with a conventional hydrochloric acid-based etching solution formed on a circuit board containing fL polar wires, Figure 4 is taken along line B-B in Figure 8. FIG. In the figure, (l) constitutes a polarization wiring at the terminal To. (2) is a substrate, (3j is an electrode wiring made of AI! or AI!-based alloy, (4) is an interlayer insulating film, (51,
tel and fyl are defects that occur in the interlayer insulating film (4), (5) is a pinhole defect, (6) is a foreign matter defect, and (7)
is a low density defect 0 copper is an insulating substrate.

なお、工TOIIIは第1図では絶縁性基板よシなる基
板12)上に形成されており、第8図では絶縁+に、裁
板端上にA/又はAl糸台金によりなる電極配線til
Jを、ぢけて回路基板(2)とし、この回路基板(2)
に形成された層間絶#虐141上に工TO(1)が形成
されている◎ このような樽成のデバイスにおいて、工TOのエツチン
グは従来、塩酸系エツチング溶液、待に塩酸と値化第2
鉄(FesCjl・5Hρ)と水を4:l:4の虚量比
で混合したものが一般によく使用されていた。オ1図、
第2図は工To薄膜を上記の4該糸エツチング浴液でエ
ツチングした例であり、基板(2)上に形成された工T
o薄膜鹸厚il 1000λ〕上にフォトレジスト等で
例えば50μm巾のパターンを形成した後、塩酸系エツ
チング溶液でエツチングした結果である。
In addition, in Fig. 1, TOIII is formed on a substrate 12) which is an insulating substrate, and in Fig. 8, electrode wiring til made of A/ or Al thread base metal is placed on the edge of the cutting board for insulation +.
Let J be a circuit board (2), and this circuit board (2)
TO (1) is formed on the interlayer breakdown 141 formed on the surface.◎ In such a barrel-formed device, etching of TO has been conventionally carried out using a hydrochloric acid-based etching solution, and then using hydrochloric acid and a valorizing solution. 2
A mixture of iron (FesCjl·5Hρ) and water at an imaginary ratio of 4:1:4 was generally used. Figure 1,
Figure 2 shows an example of etching a T film with the above-mentioned 4 thread etching bath solutions.
This is the result of forming a pattern with a width of, for example, 50 μm using photoresist or the like on a thin film with a thickness of 1000λ, and then etching it with a hydrochloric acid etching solution.

この場合s’ +%厚xoooXの工Toがジャストエ
ッチであるとき、工TOのサイドエッチは約10μm位
となり、図に示すように、きれいな配線パターンが得ら
れず、このため従来の塩酸系エツチング溶液では、パタ
ーニング可能な工T。
In this case, when the etch To with s' +% thickness xooo In solution, patterning is possible.

の称巾は、30μmが限度でこれ以下になると、itr
縁の可能性が生じる。また、第3図、オ鳴図はAl又は
AI!系合金の亀遼配線を含む回路基板に形成された工
TO薄膜を従来の塩酸系エツチング溶液でエツチングし
た例であり、Aek性基板四上に形成されたA/又はA
I!系合金よりなる゛−檀配@ 1f31 t″含む回
路基板(2)の上にSiN 4で層間絶縁物、この場合
は杷柩膜(4)を施した後、その上に工To薄膜(約x
oooffi)を形成し、これ全フォトエツチング等で
−えば6G /Imの線巾にパターニングした後、従来
の塩酸系エツチングd液でエツチングした結果である。
The nominal width is 30 μm as the limit, and if it is less than that, it
The possibility of connection arises. In addition, Fig. 3, Ome diagram is Al or AI! This is an example in which a TO thin film formed on a circuit board containing Aek-based alloy wiring was etched with a conventional hydrochloric acid-based etching solution.
I! After applying an interlayer insulator of SiN 4, in this case a loquat film (4), on a circuit board (2) containing a ``-Dan'' layer made of a ``-Dan'' type alloy, a To thin film (approx. x
This is the result of forming a pattern (oooffi), patterning it to a line width of, for example, 6G/Im by photo-etching, and then etching it with a conventional hydrochloric acid etching solution.

この場合、肋間絶縁膜(4)として用いられるSiN等
は従来成膜時あるいは成膜後に第8図、第4に示すよう
なピンホール欠陥(6)、異物欠陥(6)、及び低密度
欠陥(7)ができ、これ金避けることはほとんど不可能
である。■Toのエツチング時、これらの欠陥を通して
従来の層数系エツチング溶液が侵入し、下層のAl又は
AJ系台金よ〕なる′電極配線(3)もエツチングして
しまう。これにより1疾厚約1000人の工TOがジャ
ストエッチである場合には、下層のAlメはA/糸台金
の電極配線(alはかなりエッチオフされ、断線を生じ
ることもたびたびあった。
In this case, SiN, etc. used as the intercostal insulating film (4) conventionally suffers from pinhole defects (6), foreign object defects (6), and low-density defects as shown in FIG. 8 and 4 during or after film formation. (7), which is almost impossible to avoid. (2) When etching To, the conventional etching solution based on the number of layers penetrates through these defects, and the underlying electrode wiring (3) made of Al or AJ base metal is also etched. As a result, when a TO of approximately 1,000 people per thickness was just etched, the lower layer Al metal was considerably etched off and the electrode wiring of the A/thread base metal (Al) was often etched off, resulting in disconnection.

以上のように従来の工TOのエツチング方法では、約8
0μm以下のファインパターンが形成困難で、また下層
にAl叉はAj’系台全台金なる電極配線が形成されて
いる場合、この電極配線部もエツチングし、断線不良を
多発しやすいという欠点があった◎ 〔発明の概要〕 この究明は上記のような従来のものの欠点を除去するた
めになされたもので、基板に形成さルたh′色色層層上
形成された工TOを硫酸と硝酸を共に含む溶液でエツチ
ングすることにより、工Toのファインパターンが形成
できる方法をa供するものである。
As mentioned above, in the conventional TO etching method, approximately 8
It is difficult to form a fine pattern of 0 μm or less, and if electrode wiring is formed in the lower layer using Al or Aj' base metal, this electrode wiring part is also likely to be etched, resulting in frequent disconnections. ◎ [Summary of the invention] This investigation was carried out in order to eliminate the drawbacks of the conventional method as described above. The present invention provides a method in which a fine pattern of T0 can be formed by etching with a solution containing both.

〔発明のス施例〕[Example of invention]

以下、Cの発明の一実施vAJ’に図について説明する
Hereinafter, one embodiment of the invention of C will be explained.

第6図はこの発明の一実施例による工TOのエツチング
方法によシ形成された工TO配線を−示す部分平面図、
第6図は第5図a−C線に沿った断面図である。図にお
いて、工TO1tlrie縁性基板よシなる基板(2)
上に形成された工To741NI(1000λ)の上に
フォトレジスト%で例えば6Opm中のパターンli成
した後、硯ヨと硝酸′t−共に10重量%含む水液溶で
、その溶液温度を60℃に保ってエツチングして作成さ
れたものでりるO このJJ11合、映厚約100OA’の工TOがジャス
トエッチであるとさ、■TOのサイドエッチは約2μm
位となυす、図に示すようにシャープな配線パターンが
得られる。またパターニング可能な工Toの線巾はlo
pm位筐で可能となる0まだ、オフ図はこの究明の一実
施例による工TOのエツチング方法により形成したA7
又はAl 系合金よりなる′電極配線を何するデバイス
金示す部分平面図、第8図はオフ図D−D線に沿った断
1図であり、絶縁性基板鋼上にA/叉はAl 系合金よ
シなる電極配線(81を設けて回路基板とし、この回路
基板+21上に5iN−Jで層間絶縁ζ勿、この場合は
絶M膜(4)を施し、その後、この絶縁暎(4)上に工
To薄膜(約1ooo X )を形成し、これ?c7オ
トエツチング等でパターニングした改、例えば硫酸と硝
酸を共に10亜量%含む水液法で、その液温度t′60
℃に保ってエツチングし、パターニングされた工T O
+11 ’i得る。この場合、オフ図、第8図に示され
るような欠陥+511 +61 、 (71がノー間A
8M映(4)中に存在しても、■TOとAI!又はA/
系合金とのエッチブレイトの比が15;lであるので、
下層のAI!又はM系合金は、エツチングされず、従っ
て、M又はAl系合金よυなる゛4極配線(3)の断線
も防ぐことができる。
FIG. 6 is a partial plan view showing a TO wiring formed by an TO etching method according to an embodiment of the present invention;
FIG. 6 is a sectional view taken along line a-C in FIG. 5. In the figure, the substrate (2) is similar to the engineering TO1tlrie related substrate.
After forming a pattern of, for example, 6 Opm with photoresist % on the To741NI (1000λ) formed above, the solution temperature was heated to 60°C with an aqueous solution containing 10% by weight of both inkstone and nitric acid. This JJ11 case is made by etching with a thickness of about 100 OA', and the side etching of the TO is about 2 μm.
As shown in the figure, a sharp wiring pattern can be obtained. Also, the line width of the patternable work To is lo
The off-line diagram, which is possible with the pm-level housing, is A7, which was formed by the TO etching method according to one embodiment of this investigation.
Figure 8 is a cross-sectional view taken along the line D-D of the off-line diagram, in which A/or Al alloy is formed on an insulating substrate steel. An electrode wiring made of alloy (81) is provided to form a circuit board, and on this circuit board +21, an interlayer insulation film (4) of 5iN-J is applied, and then this insulation film (4) is applied. A thin film (approximately 1 ooo
Etched and patterned by keeping at ℃
+11 'i get. In this case, the defect +511 +61 (71 is between A
Even if it exists in the 8M movie (4), ■TO and AI! or A/
Since the etch rate ratio with the system alloy is 15;l,
Lower layer AI! Alternatively, the M-based alloy is not etched, and therefore, disconnection of the 4-pole wiring (3) due to the M or Al-based alloy can be prevented.

なお、上記夫施例では(から該と硝酸を共に1゜n<y
%含む水液法でエツチングしたが、溶液の奴度としては
、5〜50厘瀘%の硫酸と5〜50厘瀘%の硝酸を共に
含む溶液であればよく、最適−反としては共に、10〜
20重量2の硫酸と硝酸を共に含む溶液が好ましい。な
お、51真%以下では反応速度がおそくな9、エツチン
グ時間がかかりすぎる。また50厘濾%以上では硫酸で
は反部が激しくな9コントロールできなくなシ、硝酸で
は効果が偏組してしまう。また、だ液温度としては50
℃以上で、沸点以下であれ、ばよく、50℃以下では反
応速度がおそすぎて実用的でない〇 筐た上記夫施例では層間絶縁1戻m7siNとしたが、
810gあるいはB:O!/S:Nの二層にした場合で
も同様の効果が期待できる。特にslo、/81Nの二
層とすることによシピンホール欠陥(5)、低密/JC
欠陥(7)は減少させることができるが、それでも、s
@大欠陥6)ヲと9のぞくことはできないので、この発
明の工多チング方法を用いることは極めて効果的である
In the above example, both nitric acid and nitric acid were 1゜n<y
Etching was carried out using an aqueous solution method containing 5% to 50% nitric acid, but the solution strength may be any solution containing both 5 to 50% sulfuric acid and 5 to 50% nitric acid. 10~
A solution containing both 20 parts by weight of sulfuric acid and nitric acid is preferred. Note that if it is less than 51%, the reaction rate is slow9 and the etching time is too long. In addition, when the filtration rate exceeds 50%, sulfuric acid causes severe reaction and cannot be controlled, and nitric acid has uneven effects. In addition, the saliva temperature is 50
If it is above ℃ and below the boiling point, it is fine; if it is below 50 ℃, the reaction rate is too slow and it is not practical.
810g or B:O! A similar effect can be expected even when using two layers of /S:N. In particular, by using two layers of slo, /81N, pinhole defects (5), low density /JC
Defect (7) can be reduced, but still s
@Major Defects 6) and 9 cannot be overlooked, so using the multi-processing method of this invention is extremely effective.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、基板に形成された絶
縁層上に形成された工Toを硫酸と硝酸を共に含む溶液
でエツチングしたので、工Toのファインパターンが可
能となる。
As described above, according to the present invention, since the etched To formed on the insulating layer formed on the substrate is etched with a solution containing both sulfuric acid and nitric acid, it is possible to form a fine pattern of the To.

【図面の簡単な説明】[Brief explanation of drawings]

オ17は従来の工Toのエツチング方法にょシ形成され
たニーT’ O配線を示す部分平面図、第2図はオl凶
A−A線に沿った断面図、第8図は、従来υ工TOのエ
ツチング方法にょシ形成されたAl又はAl系合金の電
極配線taするデバイスを示す部分平面図、第4図はオ
8図B−B線に沿った断面図、第5図はこの発明の一実
施例による工Toのエツチング方法にょシ形成された工
TO配線を示す部分平面図、第6図は2′5図0− Q
 県に沿った断面図、オフ図はこの発明の一実施例にょ
る工TOのエツチング方法によシ形成されたAl又はA
I!系台全台金極配線を何するデバイスを示す部分平面
図、第8図はオフ図:o−D緑に沿った断面図である。 +11−−一工TO,+21−−−基板、+33−−一
電癒配線、(4)−!−絶縁膜、 なお、図中、同一符号は同−又ri−当部分を示す。 第1図 第2図 第3図 第4図 第5図 第6図 第8図 手続補正書(自発) 特許庁長官殿 1、事件の表示 特願昭 59−42511号3、補正
をする者 代表者片山仁へ部 5、補正の対象 明細書の発明の詳細な説明の欄 6 補正の内容 明細書第8頁第1θ行のr S’ : 02/ S :
 N Jをr 5in2/ SiN Jに訂正する。 以上
17 is a partial plan view showing the knee T'O wiring formed using the conventional etching method, FIG. 2 is a sectional view taken along the line A-A, and FIG. FIG. 4 is a partial plan view showing a device with electrode wiring of Al or Al-based alloy formed using the etching method of TOTO, FIG. 4 is a sectional view taken along the line B-B in FIG. FIG. 6 is a partial plan view showing the TO wiring formed by the TO etching method according to an embodiment of the present invention.
The cross-sectional view along the prefecture and the off-line view are Al or A formed by the TO etching method according to an embodiment of the present invention.
I! FIG. 8 is a partial plan view illustrating a device for which metal electrode wiring is used for all the systems. +11--1 engineering TO, +21--board, +33--1 electric healing wiring, (4)-! - Insulating film In the figures, the same reference numerals indicate the same or ri corresponding parts. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 8 Procedural amendment (voluntary) Mr. Commissioner of the Japan Patent Office 1. Indication of the case Patent application No. 59-42511 3. Representative of the person making the amendment To Hitoshi Katayama Part 5, Column 6 for detailed explanation of the invention in the specification to be amended Contents of the amendment Page 8, line 1θ r S': 02/S:
Correct N J to r 5in2/SiN J. that's all

Claims (1)

【特許請求の範囲】 111 基板に形成された絶縁物上に形成された工TO
t−硫酸と硝酸を共に含む溶液でエツチングすることを
特徴とする工TOのエツチング方法。 (2)g液は5〜50重量%の硫酸と5〜503!ji
%の硝、02ヲ共に含み、かつ溶液温度が50’C以上
で沸点以下であることを特徴とする特許請求の4囲オI
JJ記載の工Toのエツチング方法。 (31基板I′iAI!又はA!糸台金よりなる祇極配
mth−#すること全特徴とする特許請求の範囲オ1項
又は第2JJl記載の工Toのエツチング方法0
[Claims] 111 TO formed on an insulator formed on a substrate
A method for etching t-TO, characterized by etching with a solution containing both sulfuric acid and nitric acid. (2) G liquid contains 5-50% by weight of sulfuric acid and 5-503! ji
% of nitric acid, and the solution temperature is 50'C or more and below the boiling point.
Etching method of E-To described in JJ. (31 substrate I'iAI! or A! The etching method of the process according to claim 1 or 2 JJl, which is characterized in that it is entirely composed of a thread base mth-#)
JP59042511A 1984-03-05 1984-03-05 Etching method of ito Pending JPS60186020A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59042511A JPS60186020A (en) 1984-03-05 1984-03-05 Etching method of ito

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59042511A JPS60186020A (en) 1984-03-05 1984-03-05 Etching method of ito

Publications (1)

Publication Number Publication Date
JPS60186020A true JPS60186020A (en) 1985-09-21

Family

ID=12638089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59042511A Pending JPS60186020A (en) 1984-03-05 1984-03-05 Etching method of ito

Country Status (1)

Country Link
JP (1) JPS60186020A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006077241A (en) * 2004-08-25 2006-03-23 Samsung Electronics Co Ltd Etching composition for indium oxide based transparent conductive film and etching method using the same
US9868902B2 (en) 2014-07-17 2018-01-16 Soulbrain Co., Ltd. Composition for etching

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60109111A (en) * 1983-11-17 1985-06-14 三菱電機株式会社 Method of producing semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60109111A (en) * 1983-11-17 1985-06-14 三菱電機株式会社 Method of producing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006077241A (en) * 2004-08-25 2006-03-23 Samsung Electronics Co Ltd Etching composition for indium oxide based transparent conductive film and etching method using the same
US7329365B2 (en) 2004-08-25 2008-02-12 Samsung Electronics Co., Ltd. Etchant composition for indium oxide layer and etching method using the same
US9868902B2 (en) 2014-07-17 2018-01-16 Soulbrain Co., Ltd. Composition for etching
US10465112B2 (en) 2014-07-17 2019-11-05 Soulbrain Co., Ltd. Composition for etching

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