JPS60186030A - Bonding method - Google Patents

Bonding method

Info

Publication number
JPS60186030A
JPS60186030A JP59041582A JP4158284A JPS60186030A JP S60186030 A JPS60186030 A JP S60186030A JP 59041582 A JP59041582 A JP 59041582A JP 4158284 A JP4158284 A JP 4158284A JP S60186030 A JPS60186030 A JP S60186030A
Authority
JP
Japan
Prior art keywords
layer
pad
bonding
wire
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59041582A
Other languages
Japanese (ja)
Inventor
Mikio Segawa
幹雄 瀬川
Kayo Yoshida
加代 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59041582A priority Critical patent/JPS60186030A/en
Publication of JPS60186030A publication Critical patent/JPS60186030A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01515—Forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance the reliability of a bonding portion by double protecting the upper surface of a bonding pad with a pad oxide layer and the protective layer heretofore used. CONSTITUTION:An insulating layer 2 is coated on the upper surface of the substrate 1, and a pad 3 for externally connecting aluminum is formed in the pattern thereon. Then, an insulating layer 4 of refractory silicone resin having excellent properties for flattening the projection of the pad 3 is coated entirely, and a protective layer 5 of SiO2 is coated on the entire surface. Then, the layer 5 of the bonding portion and the layer 4 on the upper surface of the pad 3 are removed, a window 9 is opened, oxygen plasma is emitted to the upper surface of the pad 3 exposed in the window 9 to form an oxide (AlOx) layer 9. Then, when the one end of the fine aluminum wire 6 and the pad 3 are supersonic bonding, the oxide layer 8 of the bonding portion of the pad 3 and the wire 6 is broken by the supersonic energy, and one end of the wire 6 is pressed to the aluminum layer of the pad 3. Then, when a JCR layer 7 is formed by bonding, the surface of the pad 3 which is not pressed to the wire 6 is double protected by the layer 8, 7.

Description

【発明の詳細な説明】 （ａ）発明の技術分野 本発明はボンディング方法、特に超音波を利用した手段
等にてボンディング面に金属細線（ワイヤ）等を接続し
、パッド部分の耐湿性を向上させる方法に関する。Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a bonding method, in particular, connecting thin metal wires to a bonding surface using ultrasonic waves to improve the moisture resistance of a pad portion. Concerning how to do so.

（ｂ）技術の背景 磁気バブルメモリ素子や混成集積回路において、基板上
の回路パターンを外部接続したり、該基板にチップ状素
子を搭載又は搭載された該チップ状素子を基板回路に接
続する手段として、面と面を直接又は金属細線を介する
ボンディングが広く一般に行われている。そして、該ボ
ンディング部分の耐湿性を確保するためには、ＪＣＲ（
ジャンクション・コーティング・レジン）が塗着されて
いる。(b) Background of the technology In magnetic bubble memory devices and hybrid integrated circuits, means for externally connecting a circuit pattern on a substrate, mounting a chip-like element on the substrate, or connecting the chip-like element mounted on the substrate to a circuit on the substrate. As such, surface-to-surface bonding is commonly performed either directly or via thin metal wires. In order to ensure the moisture resistance of the bonding part, JCR (
junction coating resin) is applied.

（Ｃ）従来、技術と問題点 第１図は従来構成になる磁気バブルメモリ装置の前記ボ
ンディング部分を拡大して示す側断面図である。(C) Conventional technology and problems FIG. 1 is an enlarged side sectional view showing the bonding portion of a magnetic bubble memory device having a conventional configuration.

金属細線を用いた第１図において、１は上面にガーネッ
ト層が結晶成長されたＧＧＧ基板、２はＧＧＧ基板１の
前記ガーネット層の上に被着されたＳｉＯ□の絶縁層、
３は絶縁層２の上にＡ７！をパターン形成させた外部接
続用パッド、４はＳｉＯ□又は耐熱性シリコン…脂（ポ
リラダーオルガノシロキサン）を被着してなる絶縁層、
５はＳｉＯ□にてなる保護層、６はパッド３の上面に一
端を熱圧着したＡＰ細線、７はボンディング部分を保護
するためのＪＣＲ層である。In FIG. 1 using thin metal wires, 1 is a GGG substrate on which a garnet layer is crystal-grown; 2 is an insulating layer of SiO□ deposited on the garnet layer of the GGG substrate 1;
3 is A7 on top of the insulating layer 2! 4 is an insulating layer coated with SiO□ or heat-resistant silicone (polyladder organosiloxane);
5 is a protective layer made of SiO□, 6 is an AP thin wire whose one end is thermocompression bonded to the upper surface of the pad 3, and 7 is a JCR layer for protecting the bonding portion.

このように構成された磁気バブルメモリ装置において、
ボンディング部分はＪＣＲ層７のみによって保護されて
いるが、ＪＣＲ層７の防湿性には限界があり、ＪＣＲを
コーティングするまでの放置時間及び放置条件にによっ
て耐湿性が左右されるため、品位がばらつく欠点及び工
程管理が煩わ′しいという欠点があった。In the magnetic bubble memory device configured in this way,
The bonding area is protected only by the JCR layer 7, but there is a limit to the moisture resistance of the JCR layer 7, and the moisture resistance depends on the length of time and conditions before coating with JCR, resulting in variations in quality. There were disadvantages and process control was troublesome.

（ｄ）発明の目的 本発明の目的は、上記問題点を除去しボンディング部分
の信頼性を高めることである。(d) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned problems and improve the reliability of the bonding part.

（ｅ）発明の構成 上記目的は、磁気バブルメモリ素子や混成集積回路にお
いて、基板上にパターン形成されたポンディングパッド
を覆う保護膜を被着したのち、該保護膜に窓明けして該
パッドのポンディング面の表層部を酸素プラズマ等の手
段により酸化させ、次いで超音波を利用する等の酸化層
破壊手段により該酸化層の上から金属細線等をポンディ
ングさせることを特徴としたボンディング方法により達
成される。(e) Structure of the Invention The above object is to apply a protective film covering a patterned bonding pad on a substrate in a magnetic bubble memory element or a hybrid integrated circuit, and then open a window in the protective film to pad the bonding pad. A bonding method characterized by oxidizing the surface layer of the bonding surface using means such as oxygen plasma, and then bonding a thin metal wire or the like onto the oxidized layer by means of destroying the oxidized layer, such as using ultrasonic waves. This is achieved by

（ｆ）発明の実施例 以下に、図面を用いて本発明を磁気バブルメモリ装置に
適用した実施例を説明する。(f) Embodiments of the Invention Below, embodiments in which the present invention is applied to a magnetic bubble memory device will be described with reference to the drawings.

第２図は本発明の一実施例になる磁気バブルメモリ装置
のボンディング部分を工程順に示す図であり、第１図と
共通部分には同一符合を用いた第２図において、８はパ
ッド３の上面を酸素プラズマに曝して形成されたＡ１の
酸化（ＡｎＯｘ）層である。FIG. 2 is a diagram showing the bonding part of a magnetic bubble memory device according to an embodiment of the present invention in the order of steps. In FIG. This is an oxide (AnOx) layer of A1 formed by exposing the top surface to oxygen plasma.

第２図（イ）において、ガーネッ１−ＧＧＧ基板１の上
面に厚さ１０００人程度入金４０ｇ膜をスパッタしてな
る絶縁層２を被着さセ、その上面に厚さ５０００人程度
入金ｌの外部接続用パッド３がパターン形成される。In FIG. 2(A), an insulating layer 2 formed by sputtering a 40 g film of about 1,000 layers is deposited on the upper surface of the Garnet 1-GGG substrate 1, and a 40 g film of about 5,000 layers of deposits is deposited on the upper surface of the insulating layer 2. External connection pads 3 are patterned.

次いで第２図（ロ）に示す如く、パッド、３の突出を平
準化する性質に優れる耐熱性シリコン樹脂の絶縁層４を
スピンコードで厚さ５０００人程度入金面被着し、その
上の全面にＳｉｎ、の保護層５をスパッタで厚さ約１０
００入金度に被着形成させる。Next, as shown in Fig. 2 (b), an insulating layer 4 of heat-resistant silicone resin, which has an excellent property of leveling the protrusion of the pad 3, is applied to the deposited surface using a spin cord, and the entire surface is A protective layer 5 of Sin is sputtered to a thickness of about 10 mm.
00 deposit degree.

次いで第２図（ハ）に示す如く、パッド３の上面のボン
ディング部分の保護層５と絶縁層４を除去して窓９を穿
設したのち、窓９に露呈するパッド３の上面に酸素プラ
ズマを、例えば約１時間照射して１５０人程入金酸化（
ＡＡＯｘ）層８を形成させる。Next, as shown in FIG. 2(c), the protective layer 5 and insulating layer 4 of the bonding portion on the upper surface of the pad 3 are removed to form a window 9, and then the upper surface of the pad 3 exposed in the window 9 is exposed to oxygen plasma. For example, irradiate for about 1 hour to oxidize about 150 people (
AAOx) layer 8 is formed.

次いで第２図（ニ）に示す如く、ＡＩｌ細線６の一端と
パッド３とを超音波ボンディングすると、パッド３とＡ
ｊ２細線６との接合部の酸化層８は超音波エネルギによ
り破壊され／ｌ細線６の一端がパッド３のＡ１層に圧着
される。Next, as shown in FIG. 2(d), when one end of the Al thin wire 6 and the pad 3 are ultrasonically bonded, the pad 3 and the A
The oxide layer 8 at the junction with the j2 thin wire 6 is destroyed by ultrasonic energy, and one end of the l thin wire 6 is pressed against the A1 layer of the pad 3.

そこで第２図（ネ）に示す如く、ボッティングによりＪ
ＣＲ層７を形成させると、ＡＩ！細線６に圧着されない
パッド３の表面は、酸化層８とＪＣＲ層７により２重に
保護されるようになる。Therefore, as shown in Figure 2 (N), J
When the CR layer 7 is formed, AI! The surface of the pad 3 that is not pressed onto the thin wire 6 is doubly protected by the oxide layer 8 and the JCR layer 7.

なお、上記実施例はボッティングパッドに金属細線を超
音波ポンディングさせているが、本発明はかかる実施例
に限定されず、例えばボッティングパッドにチップ状搭
載素子を直接ボッティングさせたり、酸化層８はその形
成に際して窓９に露呈するパッド３の上面を空気中に適
宜の時間だけ曝す等の手段にて実現されるこ”とを付記
する。In the above embodiment, a thin metal wire is ultrasonically bonded to the botting pad, but the present invention is not limited to such an embodiment. The layer 8 is formed by exposing the upper surface of the pad 3 exposed to the window 9 to the air for an appropriate period of time.

（ｇ）発明の詳細 な説明した如く本発明によれば、ボッティングパッドの
耐湿性に対する従来の欠点が、ボッティングパッド上面
をパッド酸化層と従来から使用されている保護層とで２
重に保護させることにより除去され、その結果として磁
気バブルメモリ素子や混成集積回路等の特性及び信頼性
を向上し得た効果がある。(g) DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described above, the conventional drawbacks regarding the moisture resistance of the botting pad can be solved by forming the upper surface of the botting pad with a pad oxide layer and a conventionally used protective layer.
It can be removed by providing heavy protection, and as a result, the characteristics and reliability of magnetic bubble memory devices, hybrid integrated circuits, etc. can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来構成になる磁気バブルメモリ装置の素子を
その搭載基板に回路接続するボンディング部分を拡大し
て示す側断面図、第２図は本発明の一実施例になる磁気
バブルメモリ装置の素子をその搭載基板に回路接続する
ボンディング部分を工程順に示す図である。 図中において、１基板、２は基板１層の上に被着された
絶縁層、３は絶縁層２の上にパターン形成された外部接
続用バッド、４は絶縁層、５はＳｔＯ□にてなる保ｉ１
層、６はバッド３の上面に一端を熱圧着したＡＩ細線、
７はボンディング部分を保護するためのＪＣＲ層、８は
バッド３の表面に形成させた酸化層、９は絶縁層４と保
護層５を選択的に除去してなる窓である。 第　１　図 第　？　図 （イ） ？ ／ （口ンFIG. 1 is an enlarged side cross-sectional view showing a bonding part for circuit-connecting elements of a conventional magnetic bubble memory device to its mounting board, and FIG. 2 is an enlarged side sectional view of a magnetic bubble memory device according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a bonding part for circuit-connecting an element to its mounting board in order of steps. In the figure, 1 is a substrate, 2 is an insulating layer deposited on one layer of the substrate, 3 is an external connection pad patterned on the insulating layer 2, 4 is an insulating layer, and 5 is StO□. Naruho i1
Layer 6 is an AI thin wire whose one end is thermocompression bonded to the top surface of the pad 3.
7 is a JCR layer for protecting the bonding portion; 8 is an oxide layer formed on the surface of the pad 3; and 9 is a window formed by selectively removing the insulating layer 4 and the protective layer 5. Figure 1 ? Figure (a)? / (mouth)

Claims (1)

【特許請求の範囲】[Claims] 磁気バブルメモリ素子や混成集積回路において基板上に
パターン形成されたポンディングパッドを覆う保護膜を
被着したのち、該保護膜に窓明けして該バンドのボンデ
ィング面を露呈させ、該保護膜をマスクとして該ボンデ
ィング面の表層部を酸素プラズマ等の手段により酸化さ
せ、次いで超音波を利用する等の酸化層破壊手段により
該酸化層の上から金属細線等をボンディングさせること
を特徴としたボンディング方法。After depositing a protective film covering the bonding pads patterned on the substrate in a magnetic bubble memory element or hybrid integrated circuit, a window is opened in the protective film to expose the bonding surface of the band, and the protective film is removed. A bonding method characterized by oxidizing the surface layer of the bonding surface as a mask using means such as oxygen plasma, and then bonding a thin metal wire or the like over the oxidized layer by means of destroying the oxidized layer such as using ultrasonic waves. .
JP59041582A 1984-03-05 1984-03-05 Bonding method Pending JPS60186030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59041582A JPS60186030A (en) 1984-03-05 1984-03-05 Bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59041582A JPS60186030A (en) 1984-03-05 1984-03-05 Bonding method

Publications (1)

Publication Number Publication Date
JPS60186030A true JPS60186030A (en) 1985-09-21

Family

ID=12612428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59041582A Pending JPS60186030A (en) 1984-03-05 1984-03-05 Bonding method

Country Status (1)

Country Link
JP (1) JPS60186030A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5565378A (en) * 1992-02-17 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution
WO2014162387A1 (en) * 2013-04-01 2014-10-09 パイオニア株式会社 Wire connection structure and electrical device
CN106158798A (en) * 2016-07-11 2016-11-23 中航（重庆）微电子有限公司 A kind of chip structure and method for packing thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192167A (en) * 1975-02-10 1976-08-12 Handotaisochi no seizohoho

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192167A (en) * 1975-02-10 1976-08-12 Handotaisochi no seizohoho

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5565378A (en) * 1992-02-17 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution
WO2014162387A1 (en) * 2013-04-01 2014-10-09 パイオニア株式会社 Wire connection structure and electrical device
CN106158798A (en) * 2016-07-11 2016-11-23 中航（重庆）微电子有限公司 A kind of chip structure and method for packing thereof

Similar Documents

Publication Publication Date Title
JPS5851425B2 (en) Hand tie souchi
JPS6149819B2 (en)
JPH07500699A (en) Moisture sealing method for integrated circuits using silicon nitride spacers to protect the edges of oxidized passivation films
JPS62145758A (en) Method for protecting copper bonding pad from oxidation using palladium
JP2772606B2 (en) Method for forming a bump structure on an integrated semiconductor device
JPH0233929A (en) Semiconductor device
KR20040054097A (en) Bonding pad for semiconductor device and formation method of the same
JPS5795626A (en) Manufacture of semiconductor device
JPH0691126B2 (en) Semiconductor device
JPH05136198A (en) Semiconductor device
JPS5886750A (en) Semiconductor device
JPH03159125A (en) Semiconductor device
JPS617638A (en) Semiconductor device
JP2589856B2 (en) Thin film magnetic head
JPH03283630A (en) Semiconductor device
JPS6338236A (en) Semiconductor device
JPS60171616A (en) Thin film magnetic head
JPS6232636A (en) Semiconductor device
JPH02231735A (en) Semiconductor device
JPH0430533A (en) Manufacture of semiconductor device
JPS63173332A (en) Semiconductor integrated circuit device
JPH04130742A (en) Integrated circuit device
JPS62179136A (en) Semiconductor device and manufacture thereof
JPS59129433A (en) Manufacture of semiconductor device
JPS643340B2 (en)