JPS6019018B2 - data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data processing system, particularly a data processing system such as a so-called pipeline arithmetic control system, in which the contents of a read microinstruction or the contents of a partial field of the microinstruction are processed in a plurality of ways. The present invention relates to a data processing system that has a holding register that is held during a cycle, and that controls over a plurality of processing cycles based on the contents of the holding register.

Although the present invention is not limited thereto, for example, in a pipeline arithmetic control device, predetermined processing is performed on given operand data in a predetermined order, and the operand data is sequentially processed. The arithmetic control as input is executed. In such an arithmetic control device, when the arithmetic operation is controlled according to microinstructions, it is known what kind of operation will be performed in a certain processing cycle and what kind of operation will be performed in the next processing cycle. 1
If one attempts to read, decode, and execute a single microinstruction, the control required therefor becomes complicated. Furthermore, it becomes necessary to prepare microinstructions that differ slightly in control mode. SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned problems, and has the purpose of retaining the contents of a microinstruction read out from a control memory and decoded, or the contents of a partial field of the microinstruction, for example, by a shift register stage, and It is an object of the present invention to make it possible to control operations that span multiple processing cycles using microinstructions such as those described above, and to efficiently execute the above-mentioned operation control. Therefore, the data processing system of the present invention is a data processing system that includes a control memory for storing microinstructions and executes processing according to the microinstructions enigmatically issued from the control memory. A holding register that holds the contents of a partial field of the microinstruction for a plurality of processing cycles is configured in a shift register stage, and the holding register is provided with a timing counter, and the holding register holds the contents of the register in the shift register stage. The present invention is characterized in that it is configured such that it is supplied to the controlled circuit section during a corresponding processing cycle period, and the contents of the register of the relevant stage are made valid for a plurality of processing cycles by the timing counter. This will be explained below with reference to the drawings. FIG. 1 shows an example of the configuration that is the premise of the present invention, FIG. 2 shows the main part of the configuration of an embodiment of the present invention that is an improvement on the configuration shown in FIG. 1, and FIG. 3 shows the operation of the configuration shown in FIG. 2. - Show an explanatory diagram illustrating an example. In FIG. 1, 1 is a control memory, 2 is a microinstruction register, 3 is a controlled circuit section, 4A, 4C, and 4E are holding registers, and 5 to 1
0 are registers, 11 and 12 are A-series controlled circuits, 13 is a B-series controlled circuit, 14 is a C-series controlled circuit, 15 is a ○-series controlled circuit, 16 is absent, and 19 is a controlled circuit of the C series. Controlled circuits 20 to 25 of the E series each represent a gate circuit.

For example, in a controlled circuit section constituting a pipeline arithmetic control device, for example, in a processing cycle T, a circuit 13,
15 and 16 are performed, in processing cycle L, circuits 11, 14, and 17 perform calculations, in processing cycle L, circuits 12 and 18 perform calculations, and in processing cycle T3, circuit 19 performs calculations. is output.

Then, the next operand data x, is calculated by circuits 13, 15, 16 in processing cycle T, in the same way as above, and in processing cycle T2, circuits 1 1, 1
4, 17 are performed, and the processing is sequentially performed as follows. When performing the above-mentioned arithmetic processing, if the conventional method of sequentially reading and processing microinstructions that instruct control for each processing cycle from the control memory 1 is adopted as is, the processing becomes complicated and the control mode is gradually changed. Microinstructions must be prepared to make the code different.

Considering this point, in the case shown in Figure 1, for example, one microinstruction is divided into multiple fields A, B, C, D, E, etc., and a shift register stage is set up corresponding to each field. The holding registers 4A, 4C, 4E, etc. that constitute the memory are prepared in advance.

Then, the microinstruction set in the microinstruction register 2 is decoded and controlled as follows. That is, {1- In the processing cycle To, the circuit 13 is activated by the contents of field B, the circuit 15 is activated by the contents of field D,
The contents of field E control the circuits 16 respectively.

'21 Then, the gate circuits 20, 21, and 22 are turned on to set the contents of field A in register 5, the contents of field C in register 7, and the contents of field E in register 8.

{31 In processing cycle T, circuit 11 is activated according to the contents of register 5, and circuit 1 is activated according to the contents of register 7.
4 and 17 are controlled by the contents of register 8, respectively.

(2) Gates 23 and 24 are then turned on to set the contents of register 5 to register 6 and the contents of register 8 to register 9.

'51 In processing cycle T2, circuit 12 is activated according to the contents of register 6, and circuit 1 is activated according to the contents of register 9.
8 respectively.

[61] Then, the gate 25 is turned on and the contents of the register 9 are set in the register 10.

'71 In processing cycle T3, the circuit 19 is controlled by the contents of the register 10.

In the case shown in FIG. 1, when the above-mentioned arithmetic processing is sequentially executed on operand data given one after another, the same microinstruction is issued from the control memory 1 for each processing cycle and stored in the microinstruction register. It is only necessary to set it to 2, which greatly simplifies the arithmetic control.

Of course, in general, the arithmetic processing in a pipeline arithmetic and control device is not necessarily as simple as shown as the controlled circuit section 3 in FIG. Then, a certain type of calculation mode (if a
), for example, the C-series calculations are omitted, or in some cases, the A-series calculations are omitted. In such a case, the corresponding microinstruction may be considered to be such as setting the contents of field C to an empty state or setting the contents of field A to an empty state. By adopting the configuration shown in FIG. 1, calculation control is greatly simplified as described above.
Considering the case where the arithmetic processing based on the illustrated circuits A2 and E2 is executed continuously or intermittently over multiple processing cycles, and then the arithmetic processing based on the circuit E3 is performed. Problems arise, such as an undesirable increase in the number of shift register stages.

FIG. 2 shows a main part of the structure of an embodiment of the present invention that solves this problem, and only shows the structure of the holding register 4E in the structure shown in FIG.

The numbers 2, 4E, 8, 9, 10, 24, and 25 in the figure are the first
Corresponding to the figure, 26, 27, and 28 are counters that are incremented and incremented in accordance with the processing cycle and output their outputs according to the program, and 29, 30, and 31 represent AND counters, respectively. . By employing the configuration as shown in FIG. 2, it becomes possible to program the counters 26, 27, and 28 to perform processing as shown in FIG. 3, for example.

FIG. 3 illustrates the following case as an example.

That is, (i) when the microinstruction 1 is set in the register 8, the counter 26 outputs logic "1" when the count value "1 mountain" is "2", and the gate 24 outputs the logic "1" when the count value "1" is "2".
(ii) When microinstruction 3 is set in register 8 without being set in register 8 for microinstruction 2, the counter 26 has a count value of "0".
(5i) When the microinstruction 1 is set in the register 9, the counter 27 outputs the logic "1" at the count value "0" and turns on the gate 24.
1" and turns on the gate 25. (i) When the microinstruction 3 is set in the register 9, the counter 2
7 outputs logic "1" at count value "0" and turns on gate 25, and (U) when microinstruction 1 is set in register 10, counter 28 outputs logic "1" at count value "0". When the microinstruction 3 is set in the register 10, the counter 28 is shown as outputting a logic "1" when the count value "1" is "2". Note that the counters 26, 27,
It goes without saying that control over 28 can be fixedly determined or can be controlled based on the contents of field E.

As explained above, according to the present invention, processing using microinstructions is greatly simplified in cases where, for example, in a pipeline arithmetic control device, once one arithmetic mode is determined first, known arithmetic devices are sequentially executed. This makes it possible to reduce the number of shift register stages.

[Brief explanation of drawings]

FIG. 1 shows an example of the configuration that is the premise of the present invention, FIG.
The figure shows an explanatory diagram for explaining an example of the operation of the configuration shown in FIG. In the figure, 1 is a control memory, 2 is a microinstruction register, 3 is a controlled circuit section, 4A, 4C, and 48 are holding registers, respectively.
5 to 10 each represent a register forming a shift register stage, and 26, 27, and 28 each represent a counter. Ryo24na3471 mother

Claims (1)

[Scope of Claims] 1. In a data processing system that includes a control memory for storing microinstructions and executes processing according to microinstructions read from the control memory, the contents of the read microinstructions or the microinstructions are A holding register that holds the contents of a partial field for a plurality of processing cycles is composed of a shift register stage, and the holding register is equipped with a timing counter, and the holding register holds the contents of a partial field of
The contents of the registers in the register stage are supplied to the controlled circuit section during the corresponding processing cycle period, and the timing
A data processing system characterized in that a counter is configured to validate the contents of a register at a stage for a plurality of processing cycles. 2. The controlled circuit unit sequentially performs predetermined processing on given operand data in a predetermined order, and the operand data is sequentially inputted. The data processing system according to scope 1.