JPS60193397A - Ceramic multilayer circuit board - Google Patents

Ceramic multilayer circuit board

Info

Publication number
JPS60193397A
JPS60193397A JP4993784A JP4993784A JPS60193397A JP S60193397 A JPS60193397 A JP S60193397A JP 4993784 A JP4993784 A JP 4993784A JP 4993784 A JP4993784 A JP 4993784A JP S60193397 A JPS60193397 A JP S60193397A
Authority
JP
Japan
Prior art keywords
conductor layer
layer
ceramic multilayer
weight
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4993784A
Other languages
Japanese (ja)
Inventor
三森 誠司
堀部 芳幸
尭島 秀次
宮 好宏
上山 守
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP4993784A priority Critical patent/JPS60193397A/en
Publication of JPS60193397A publication Critical patent/JPS60193397A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (発明の属する技術分野) 本発明はセラミック多層配線板の改良に関する。[Detailed description of the invention] (Technical field to which the invention pertains) The present invention relates to improvements in ceramic multilayer wiring boards.

(従来技術とその問題点) 従来のセラミック多層配線板(以下配線板という)はセ
ラミック基板上KMo、W等を主成分とした導体ペース
トを塗布して#11の導体層を形成し、その上面にスル
ーホールを有する絶縁層を形成し、さらKその上面と前
記スルーホールKAg。
(Prior art and its problems) In a conventional ceramic multilayer wiring board (hereinafter referred to as a wiring board), a #11 conductive layer is formed by coating a conductive paste mainly composed of KMo, W, etc. on a ceramic substrate. An insulating layer having a through hole is formed on the upper surface thereof and the through hole KAg.

Au等の貴金属ペーストを塗布して第2の導体層を形成
して作成するのが一般に知られている。
It is generally known to form a second conductor layer by applying a noble metal paste such as Au.

しかし上記のような手法にて作成する配線板は第2の導
体層を大気中で焼結させるため第1の導体層が酸化し易
いという欠点がある。
However, the wiring board produced by the method described above has the disadvantage that the first conductor layer is easily oxidized because the second conductor layer is sintered in the atmosphere.

この対策として中性又は還元性雰囲気中で焼成する手法
がるるか、この手法では中性又は還元性雰囲気にするた
めの費用がかかる。すなわち製造コストが高゛いという
火点がめる。
As a countermeasure to this problem, there is a method of firing in a neutral or reducing atmosphere, but this method requires the expense of creating a neutral or reducing atmosphere. In other words, the problem is that manufacturing costs are high.

(発明の目的) 本発明はこれらの欠点のない配線板を提供することを目
的とするものでるる。
(Object of the Invention) The object of the present invention is to provide a wiring board free from these drawbacks.

(問題点を解決するための手段)′ 本発明者らは上記の欠点について種々検討した結果、高
融点金属を主成分とする第1の導体層とAg/Pdから
なる第2の導体層との間の絶縁層間のスルーホールに不
活性金属層を形成することにより大気中で焼成しても第
1の導体層が酸化しないことを確認した。
(Means for Solving the Problems)' As a result of various studies on the above-mentioned drawbacks, the present inventors found that a first conductor layer containing a high melting point metal as a main component and a second conductor layer consisting of Ag/Pd. It was confirmed that by forming an inert metal layer in the through hole between the insulating layers, the first conductor layer would not be oxidized even when fired in the atmosphere.

(発明の構成) 本発明は高融点金属を主成分とする第1の導体層とAg
/Pdからなる第2の導体層との間の絶縁層間のスルー
ホールに不活性金属層を形成してなる配線板に関する。
(Structure of the Invention) The present invention provides a first conductor layer containing a high melting point metal as a main component and an Ag
The present invention relates to a wiring board in which an inert metal layer is formed in a through hole between an insulating layer and a second conductor layer made of /Pd.

(材料例) なお本発明において高融点金属としてはMo、W等が用
いられ、不活性金属としてはPi、Pd、Rh等比較的
高融点の貴金属が用いられる。不活性金属層は無電解め
っき、電解めっき、蒸着等の方法により形成される。
(Material Examples) In the present invention, Mo, W, etc. are used as high melting point metals, and noble metals with relatively high melting points such as Pi, Pd, Rh, etc. are used as inert metals. The inert metal layer is formed by methods such as electroless plating, electrolytic plating, and vapor deposition.

木兄明忙おける第1の導体層とは配線板の内側(セラミ
ック基板に近い位置)に形成する導体層で、第2の導体
層とは表面に露出する導体層である。
The first conductor layer in the board is a conductor layer formed inside the wiring board (near the ceramic substrate), and the second conductor layer is a conductor layer exposed on the surface.

第1の導体層は1層でもよく多層構造としてもよく特に
制限はない。また本発明では第1の導体層と不活性金属
層との間に他の導体金属層を形成してもよい。
The first conductor layer may have a single layer or a multilayer structure, and is not particularly limited. Further, in the present invention, another conductive metal layer may be formed between the first conductive layer and the inert metal layer.

(実施例) 以下実施例により本発明を説明する。(Example) The present invention will be explained below with reference to Examples.

実施例1 アルミナメ96重量%、シリカ2.0重量%、カルシア
1.0重量%およびマグネシア1.0重量%を配合し9
次に前記組成物1oo重量部に有機バインダーとしてポ
リビニルブチラール性0重量部。
Example 1 96% by weight of aluminium, 2.0% by weight of silica, 1.0% by weight of calcia and 1.0% by weight of magnesia
Next, 0 parts by weight of polyvinyl butyral as an organic binder was added to 10 parts by weight of the composition.

可塑剤としてDOPを4.0重量部および有機溶剤トシ
てトリクロールエチレンとメチルアルコールの共沸混合
物50重量部を添加して均一に混合し。
4.0 parts by weight of DOP as a plasticizer and 50 parts by weight of an azeotropic mixture of trichlorethylene and methyl alcohol were added to the organic solvent and mixed uniformly.

ついでドク・ターブレード法により厚さ0.8 mmの
セラミックグリーンシートを得た。
Then, a ceramic green sheet with a thickness of 0.8 mm was obtained by the Doc Turblade method.

一方上記とは別に平均粒径が2μmと0.5μmのW(
タングステン)粉をそれぞれ60重量%。
On the other hand, apart from the above, W (
60% by weight of each powder (tungsten).

40重量%配合し、このW粉100重量部に有機30重
量部を添加して均一に混合してWペーストを得た。
40% by weight was blended, and 30 parts by weight of organic material was added to 100 parts by weight of this W powder and mixed uniformly to obtain a W paste.

次に前述のセラミックグリーンシート上に前述のWペー
ストをスクリーン印刷し、その上面に上記のセラミック
グリーンシートと同組成の絶縁ペーストを直径0.2 
mmのスルーホールを残して印刷した後PH5O/ P
Ht = 0.45の弱還元性疎囲気中で1時間200
℃の昇温速度で1560’Cに昇温し。
Next, the above-mentioned W paste was screen printed on the above-mentioned ceramic green sheet, and an insulating paste having the same composition as the above-mentioned ceramic green sheet was applied on the top surface with a diameter of 0.2 mm.
PH5O/P after printing leaving a mm through hole
200 for 1 hour in a weakly reducing atmosphere with Ht = 0.45
The temperature was raised to 1560'C at a temperature increase rate of 150°C.

1560℃で1時間保持して焼成した後1時間300℃
の速度で降温して第1の導体層および絶縁層を形成した
セラミック基板を得た。
Hold at 1560℃ for 1 hour and then bake at 300℃ for 1 hour.
A ceramic substrate on which a first conductor layer and an insulating layer were formed was obtained by decreasing the temperature at a rate of .

次に通常の湿式めっき方法忙従い上記の焼結し・たセラ
ミック基板を活性化処理した後、スルーホールにより露
出した第1の導体層上に無電解のPtめつきを5μmの
厚さに施し、ついで洗浄、乾燥後H1雰囲気中で950
℃で20分熱処理した。
Next, after activating the above sintered ceramic substrate using the usual wet plating method, electroless Pt plating is applied to a thickness of 5 μm on the first conductor layer exposed through the through hole. , then washed and dried at 950°C in an H1 atmosphere.
Heat treatment was performed at ℃ for 20 minutes.

さらに前述の絶縁層上およびスルーホールのPtめっき
層上にAg/Pd厚膜ペースト(日中マツセイ製、商品
名TR−4846)をスクリーン印刷し、それを大気中
で900℃で10分熱処理して第2の導体層を形成して
配線板を得た。
Furthermore, an Ag/Pd thick film paste (trade name: TR-4846, manufactured by Matsusei Corporation, Japan) was screen printed on the above-mentioned insulating layer and the Pt plating layer of the through holes, and it was heat-treated at 900°C for 10 minutes in the air. A second conductor layer was formed to obtain a wiring board.

実施例2 Ptめつきを施した後のル雰囲気中での熱処理を行なわ
ない以外は実施例1と同一の組成および同一の工程を経
て配線板を得た。
Example 2 A wiring board was obtained using the same composition and the same steps as Example 1, except that the heat treatment in the atmosphere after Pt plating was not performed.

実施例3 ptめつきを施す前にNiめっきを3μmの厚さに施し
た以外は実施例1と同一の組成および同一の工程を経て
配線板を得た。
Example 3 A wiring board was obtained using the same composition and the same steps as Example 1, except that Ni plating was applied to a thickness of 3 μm before PT plating.

次に実施例1.2および3で得た配線板について観察し
たところ第1の導体層の酸化は見られなかった。これは
不活性金属層が第1の導体層上に密着して遮へい膜とな
り酸素が直接第1導体に接触しない構造にしたためでる
るものと考える。
Next, when the wiring boards obtained in Examples 1.2 and 3 were observed, no oxidation of the first conductor layer was observed. This is thought to be due to the structure in which the inert metal layer adheres closely to the first conductor layer and acts as a shielding film so that oxygen does not come into direct contact with the first conductor.

(発明の効果) 本発明は高融点金属を主成分とする第1の導体層とAg
 /Pdからなる第2の導体層との間の絶縁層間のスル
ーホールに不活性金属を形成するので。
(Effects of the Invention) The present invention provides a first conductor layer containing a high melting point metal as a main component and an Ag
This is because an inert metal is formed in the through hole between the insulating layer and the second conductor layer made of Pd.

#Ilの導体層は酸化せず、また大気中で第2の導体層
の焼結ができるため安価な配線板を得ることができる。
Since the #Il conductor layer does not oxidize and the second conductor layer can be sintered in the atmosphere, an inexpensive wiring board can be obtained.

第1頁の続き 0発 明 者 上 山 守 日立市東町4究所内Continuation of page 1 0 shots Akira Kamiyama Mamoru Hitachi City Higashimachi 4th Institute

Claims (1)

【特許請求の範囲】[Claims] 1、高融点金属を主成分とする第1の導体層とAg、/
Pdからなる第2の導体層との間の絶縁層間のスルーホ
ールに不活性金属層を形成してなるセラミック多層配線
板。
1. The first conductor layer mainly composed of a high melting point metal and Ag, /
A ceramic multilayer wiring board in which an inert metal layer is formed in a through hole between an insulating layer and a second conductor layer made of Pd.
JP4993784A 1984-03-15 1984-03-15 Ceramic multilayer circuit board Pending JPS60193397A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4993784A JPS60193397A (en) 1984-03-15 1984-03-15 Ceramic multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4993784A JPS60193397A (en) 1984-03-15 1984-03-15 Ceramic multilayer circuit board

Publications (1)

Publication Number Publication Date
JPS60193397A true JPS60193397A (en) 1985-10-01

Family

ID=12844937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4993784A Pending JPS60193397A (en) 1984-03-15 1984-03-15 Ceramic multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS60193397A (en)

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