JPS60200564A - Thin film semiconductor element integrated circuit device - Google Patents

Abstract

PURPOSE:To simply form a wiring construction by connecting an active region through a conductive film passing an insulating film with a conductive substrate, thereby reducing the area of the substrate. CONSTITUTION:In an electric circuit having a plurality of thin film semiconductor elements having active regions 31a to be disposed at the common prescribed potential as constituents is partly formed on the surface of an insulating film 20 formed on the surface of a conductive substrate 10, the regions 31a of these thin film semiconductor elements are respectively connected with the substrate 10 via conductive films 151 passing the film 20. Thus, wiring films commonly connected with the regions 31a can be eliminated to reduce the area of the substrate and to simplify the wiring construction.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a method for forming an electric circuit including a plurality of thin film semiconductor elements (1! component) on the surface of an insulating film formed on the surface of a conductive substrate. The present invention relates to a thin film semiconductor element integrated circuit device.

[Prior art]

Figure 1 (4) shows 0M using a thin film MOS transistor.
FIG. 2 is a plan view of main parts showing an example of a conventional thin film semiconductor element integrated circuit device configured with an 0E+ inverter circuit.

FIG. 1(B) is a sectional view taken along line IB--IB in FIG. 1(A), and FIG. 1(0) is a sectional view taken along line IC-10 in FIG. 1(4). The illustration of the 0M0S inverter is omitted.

In the figure, QO is a conductive substrate made of a conductor or semiconductor, (1) is an insulating film formed on the surface of the conductive substrate 00, and OB and 61) are horizontally formed on the surface of the insulating film (E). C! of the first stage of the CMOS inverter chain circuit are formed into island shapes with intervals between them. M.O.S.
n-channel MO8 transistor (
A p-type polycrystalline semiconductor layer (hereinafter referred to as ip-type polycrystalline layer) for forming a p-type polycrystalline semiconductor layer (hereinafter referred to as rn-MO8TJ) and a p-channel MO8) transistor (hereinafter referred to as rp-MO8T)
n-type polycrystalline semiconductor layer (hereinafter referred to as "n-type polycrystal"), (31a) and (31b) for forming an n-type polycrystalline semiconductor layer (referred to as "J")
(41a) are the n-type source region and n-type drain region of the n-MO8T of the first-stage 0M0S inverter, which are formed by diffusing n-type impurities into both lateral ends of the p-type polycrystalline layer OD, respectively; (41b) is n-type polycrystalline layer II)
The p-MO8T p-MO8T of the first stage 0M0S inverter is formed by diffusing p-type impurities into both lateral ends of the p-MO8T.
type source region and p type drain region, (a) and (
6) is formed in the form of an island on the surface of the insulating film (e) between the p-type polycrystalline layer 01) and the n-type polycrystalline layer 0) at intervals in the vertical direction. A p-type polycrystalline layer for forming the n-MO8T constituting the second-stage CMOS inverter and an n-type polycrystalline layer for forming the p-MO8T, (3Za) and (32b)
) are respectively n at both lateral ends of the p-type polycrystalline layer (a).
The second stage C formed by diffusing shape impurities! The n-type source region and n-type drain region (42a) and (421)) of the n-MO8T of the MOS inverter are formed by diffusing p-type impurities into both lateral ends of the n-type polycrystalline layer (6), respectively. p-MO of the second stage 0M0S inverter
8T p-type source and p-type drain regions, (51
) and (61) are polycrystalline semiconductor layers, and n-type source/drain regions (31a) and (3
p of the n-type polycrystalline layer θυ on the surface of the part between 1b)
A gate insulating film (51a) is formed on the surface of the portion between the source/drain regions (ala) and (a, 1b) of the shape.
and the first stage CMOS formed through (61a)
The gate electrode of the n-MO8T of the inverter and the p-
Gate electrode of MOST, (52) and (62)
is a polycrystalline semiconductor layer, and is formed on the surface of the portion between the n-type source/drain regions (32a) and (32b) of the six p-type polycrystalline layers and on the p-type source of the n-type polycrystalline layer (6).・The n-MO8T gate of the second stage 0M0S inverter is formed on the surface of the portion between the drain regions (42a) and (42b) via the gate insulating film (52a) and the gate insulating film (62a), respectively. Electrodes and p-MOE
The IT gate voltage ti, (71) is a polycrystalline layer C32 of the second-stage CMOS inverter with respect to the polycrystalline layer Gυ,C] of the first-stage CMOS inverter on the surface of the insulating film layer made of a polycrystalline semiconductor layer. , formed on the part opposite to the 12 side and the first stage 0M0E! Inverter n-MO8T gate voltage [x (51) and p-MO8T gate → gate voltage FM
(61) and has an input pad connection portion (71a) to which an input terminal connection pad (described later) is connected.

(72) is a polycrystalline semiconductor film, and the polycrystalline NIOυ, θp of the first stage 0M0S inverter on the surface of the insulating film (e)
and the polycrystalline layer of the second stage CMOS inverter (a), ni)
n −M OEI T (T) gate lightning @ (52
) and rMeD-MO8T 17) Gate electrode (62)
A first-stage MO8T connection film connection part (2a) to which the first-stage MO8T connection film described below is connected in common, and a first-stage output take-out wiring to which the first-stage output take-out wiring film described below is connected. The first stage output wiring film (73) is a polycrystalline semiconductor film having a film connection part (72b) and an insulating film (1).
) Polycrystal of the second stage CMOS inverter (a)
) and the third-stage CMOf3 inverter (not shown), and the gate electrode of the n-MO8T (not shown) of the third-stage QMO8 inverter and the p-MO8T
A second stage MO8 is commonly connected to the gate electrode (not shown) of the second stage MO8, and a second stage MO8T connection film, which will be described later, is connected to the second stage MO8.
The T continuous membrane connection part (73a) and the second stage output wiring film connection part (v3) to which the second stage output wiring film described later is connected.
b), the second stage output wiring film (SO) is an insulating film (
On the surface of 4), the polycrystalline layer Gυ, (to), 61) , (
6) on the surface of the gate electrode (51) 1 (52) l
(61) l On the surface of (62) and wiring film (71)
, ()2), an interlayer insulating film formed over the surfaces of (73), , (90) is an input pad connection portion ('
Regarding 71a), the polycrystalline layer c3 of the first stage CMOS inverter is formed on the surface of the part opposite to the (41) side, and the input wiring film ('11) of the interlayer insulating film ((a))
An input terminal connection pad that is connected to the input pad connection part ('71a) through a contact hole (8)la) provided in the upper part of the input pad connection part (71a) of , (100) is an n-type source region (31a) of n-MO8T of the first stage CMOS inverter, which is made of a metal film and has an interlayer insulating film (80).

On the surface of the n-type source region (32a) of the n-MO8T of the second-stage 0M0S inverter and the upper portion of each n-type source region (not shown) of the n-MO8T of the third-stage and subsequent CMOS inverters. These n-type source regions (31a) of the interlayer insulating film (80) are formed so as to pass through the interlayer insulating film (80).
, (32a), ---- contact hole (831m) provided on the surface of the upper part of each, (
832a), -1- through the n-type source region (31
A vss terminal connection pad (101) is formed to connect the vss terminal (normally zero position) to the end on the input terminal connection pad (90) side.
The ss wiring film (110) is a metal film and is an interlayer insulating film (
80) p-type drain region (41b) of p-MO8T in the first-stage CMOS inverter, p-type drain region (a2b) of p-MO8T in the second-stage 0M0S inverter
and p-MO8T of CMOS inverter from 3rd stage onwards
The eyebrow insulating film (80
) of these p-type drain regions (41b), (4gb)
---Contact holes (s41b) and (a4ab) provided on the surface of the upper part of each of the contact holes (s41b) and (a4ab).

- p-type drain region (411) through 111),
(421)), ---1c is connected and a vDD terminal connection pad (LLl) is formed at the end on the input terminal connection pad (90) side to connect a VY terminal (normal voltage potential).
) D wiring film, (121) is an interlayer insulating film (
80) is formed over the surface of the portion above the n-type drain region (slb) of the n-MO8T and the surface of the portion above the p-type source region (4Xa) of the p-MO8T of the first stage 0M0S inverter. n through contact holes (831b) and (841&) provided in the interlayer insulating film ((a)) above these n-type drain regions (31b) and above the p-type source regions (41a), respectively. The first stage MO8T connection film connection part (72a) of the first stage output wiring HIE ('72) is connected to the type drain region (31b) and the p-type source region (41a) and is of the interlayer insulating film ((a)). The first stage MO8T connection film 1 is connected to the first stage MO8T connection film connection part ('72a) through the contact hole (s72a) provided in the upper part.
．． (122) is a metal film on the surface of the interlayer insulating film (80) above the n-type drain region (32b) of the n-MO8T of the second stage CMOS inverter and on the p-M
It is formed over the surface of the part above the p-type source region (4Za) of O8T, and is formed over the part of the glabella insulating film (80) above these n-type drain regions (3zb) and above the p-type source region (42a). The n-type drain region (32b) and the p-type source region (
42a) and the second stage MO8T connection film connection part (7) of the second stage output wiring film ('73) of the interlayer insulating film (80).
Contact hole (s7) provided in the upper part of 3a)
sa) through the second stage MO8T connection membrane connection part (73a
) The second stage MO8T connection film (131) is a metal film and is connected to the first stage output wiring film (131) of the interlayer insulating film (80).
The glabella insulating film (21)) is formed on the surface of the part extending from the upper part of the first stage output wiring film connection part (21)) to the side opposite to the first stage output wiring film (72). b)) Connected to the first stage output wiring film connection part (V2b) through the contact hole (8) 21)) provided in the upper part of the first stage output takeout wiring film connection part (72t)). The first stage output wiring film (132) is a metal film, and is connected from the upper part of the second stage output wiring film (73) of the second stage output wiring film (73) of the interlayer insulating film (80). 2
It is formed on the surface of the part extending to the side opposite to the stage output wiring film (73) side, and is provided on the part above the second stage output take-out wiring film connection part ('73b) of the glabella insulating film (80). This is the second stage output wiring film connected to the second stage output wiring film connection part ('/3b) through the contact hole (8'/3'b).

Next, the operation of the conventional example configured as described above will be explained.

First, set the potential of the v8B terminal connection pad (sword 1) to zero.

The potential of the VDD terminal connection pad (111) is set to positive V-.

In this state, the input terminal connection pad (90)
When the potential of the first stage 0M0S inverter becomes zero, n
- MOET gate voltage fM (51) and p-MOE
Since the potential of the gate electrode (61) of T becomes zero, n-M
Since OET is in the OFF state and p-MOET is in the ON state, the potential of the first stage MO8T connection film (121) is 1
The potential of the output wiring film (72) in the first stage and the potential of the output wiring film (131) in the first stage become vDD. Then, when the potential of the first-stage output wiring film (72) becomes vDD, the gate electrode (5) of the n-MOET of the second-stage OMOS inverter becomes
2) and the gate voltage ffi of p-MOET, (62)
The potential at which the potential becomes vDD, the second stage output wiring film (73
) and the potential of the second stage output lead-out wiring film (unit 2) become zero.

Moreover, when the potential of the input terminal connection pad (90) is set to vDD, the first stage MO8T connection llα is reversed to the above case.
(121), the potential of the first stage output wiring film (2), and the potential of the first stage output wiring film (131) become zero.

The potential of the second-stage MO8T connection [11 (122), the potential of the second-stage output wiring film (3), and the potential of the second-stage output wiring film (132) become v])D.

In this way, when a binary number with a zero potential of 10'' and a vDD potential of 1.1'' is input to the input terminal connection pad (90), the input terminal connection pad ( A binary sign opposite to the input binary signal to the input terminal connection pad (90) is obtained, and a binary sign similar to the input binary signal to the input terminal connection pad (90) from the even-numbered stage output wiring film is obtained. can get.

By the way, in this conventional example, the 0M0E! When the number of inverter stages increases, for example, the length of the Vss wiring film (100) becomes longer, so that each n-M'OS T in which the vss wiring film (lOO) is commonly connected from the ss terminal connection pad (101) Due to the difference in the distance to the n-type source regions (31a), (32a), ---1, that is, the difference in resistance, the potential of these n-type source regions (31a), (32a), --m-
A difference is created due to the current flowing through the ss wiring film (cooo).

Therefore, in order to reduce such potential difference, v
Since the lateral width of the 88 wiring film (100) must be increased to reduce the resistance of the v8s wiring film (xyo)-, there is a drawback that the substrate area becomes large.

In addition, since the output wiring films (131) and (132L---1) for taking out the output of the CMOS inverters of each stage intersect with the ss wiring film (100), these output wiring films (131) , ('132), ---- must be wired with the eyebrow insulating film (80) interposed between it and the vss wiring film (100), so there is also the drawback that the wiring configuration becomes complicated. Ta.

[Summary of the invention]

The present invention was made with the aim of eliminating the above-mentioned drawbacks, and consists of a plurality of active regions each having a predetermined common potential on the surface of an insulating film formed on the surface of a conductive substrate. In a device in which an electric circuit is formed using a thin film semiconductor element as a component.

By connecting the active regions of these thin film semiconductor devices to a conductive substrate through conductive films that penetrate through the insulating film, the substrate area can be reduced and the wiring configuration can be simplified. A thin film semiconductor element integrated circuit device is provided.

[Embodiments of the invention]

Figure 2 (4) shows CMO using a thin film MO8) transistor.
FIG. 2(B) is a plan view of main parts showing the thin film semiconductor element integrated circuit device of the first embodiment of the present invention, which constitutes an S inverter chain circuit. Cross-sectional view, foil Figure 2 (0) is a cross-sectional view taken along the ■q-Ic line in Figure 2 (A).The illustration of the C!MOS inverters in the third and subsequent stages of the oMos inverter chain circuit is omitted. .

In the figure, the same symbols as those shown in FIG. 1 indicate equivalent parts. In addition, in this embodiment, the active regions that should be at a common predetermined potential of a plurality of thin film semiconductor elements are the n-type source region (31a) of the n-MOET of the CMOS inverter at each stage,
(32a),---1.

Now, (141) is the glabella insulating film (80) and the insulating film (
b) of the first stage 0M08 inverter n-MOET n
type source region (31a), n-type drain region (3xb
) side is an n-type source region (31
The contact hole (142) is provided parallel to the n-type source region (31a) with a distance between the contact hole (142) and the n-type source region (31a).
Similarly to the contact hole (141), the second stage OMO
n-type source region (32a) of n-MOBT of S inverter
), a contact hole provided in the vicinity of (1
51) is a contact hole (831a) on the surface of the interlayer insulating film (80).

(141), and one side is connected to the n-type source region (31a) through the contact hole /l/ (s3ia), and the other side is connected to the conductive substrate 00 through the contact hole (141). A metal film (152), which is a conductive film in this example and is connected to the metal film (151), is formed on the surface of the first interlayer insulating film (80), and one side thereof has a contact hole ( 83
The metal film (161) is connected to the n-type north region (32a) through 2a), and the other side is connected to the conductive substrate α0 through the contact hole (142), and is the conductive film in this example. On the surface of the interlayer insulating film (80) made of a metal film, one end is connected to the connection part of the first stage MO8T connection film (121) with the first stage output wiring film (72), and the other end is connected to the connection part with the first stage output wiring film (72). The first stage output take-out wiring film is formed to extend in the direction of the metal IJ (Mal) side, (
162) is made of a metal film, and one end is connected to the second MOEIT connection film (122) on the surface of the interlayer insulating film (80).
This is a second-stage output wiring film connected to the connection portion with the second-stage output wiring film (73) and formed so that the other end extends in the direction toward the metal film (positive 2) side. Note that Figure 5 is not shown.

For CMOS inverters from the third stage onwards, metal film (
151) l (easy 2) and output take-out wiring film (16
1) A metal film and an output wiring film similar to those in (162) are formed.

In this example, the potential of the conductive substrate (1υ is set to zero, and
If the potential of the input terminal connection pad (111) is set to positive V, the input terminal connection pad (90) is set to zero potential and the VDD potential is set to "0", as in the conventional example shown in FIG.ゝl“
When a binary number is inputted, a binary number opposite to the input binary signal from the output wiring film of the odd-numbered stage to the input terminal connection pad (90) is obtained, and the number of outputs of the even-numbered stage is A binary code similar to the input binary signal from the output wiring film to the input terminal connection pad (bright) is obtained.

Moreover, (even if the number of CMOS inverter stages that make up the 3MOS inverter chain circuit increases, the CMOS
The n-type source region (31a,
).

(32a), ---one is a metal film (151), respectively.
(152) and ---- are connected to the conductive substrate α0, so these n-type source regions (31a
), (32a), there is no difference in potential between -1-.

In addition, as in the conventional example shown in FIG.
Since O) is not required, the board area can be made smaller than that of the conventional example, and the wiring structure can be made simpler than that of the conventional example.

Chopsticks Figure 3 (4) uses a thin film MO8 transistor to generate 0M0
FIG. 3(B) is a plan view of main parts showing a thin film semiconductor element integrated circuit device according to a second embodiment of the present invention, which constitutes an S inverter circuit. 3(0) is a sectional view taken along the line ■a--e in FIG. 3(4). Note that illustration of the CMOS inverters in the third and subsequent stages of the 0M0S inverter chain circuit is omitted.

In the figures, the same symbols as those shown in Figures 1 and 2 indicate equivalent parts, ) (loa) is a conductive substrate made of a conductor, and (171) is the first stage of the insulating film (e). 0M0
The n-type source region (31a) of the n-MOBT of the S inverter
) contact hole provided in the lower part (172
) is the n-type source region of the n-MOBT of the second stage CMOS inverter (
Contact hole provided in the lower part of 32a).

(181) is made of an n-type polycrystalline semiconductor or an in-type amorphous semiconductor, and is formed in the contact hole (171), and one end surface is connected to the n-type source region (31a), and the other end surface is connected to the conductor substrate (31a). The n-type semiconductor film, (1B2), which is connected to lOa) and is the conductive film in this example.

Similar to the n-type semiconductor film (181), the contact hole (
1'72) and one end face is an n-type source region (
32a) and the other end surface is connected to the conductive substrate (LOA), which is the conductive film in this embodiment.
It is a shaped semiconductor film.

This embodiment also has the same effects as the first embodiment shown in FIG.

Figure 4 (Chrysanthemum is 0M0S using thin film MO transistor)
A plan view of main parts showing a thin film semiconductor element integrated circuit device according to a third embodiment of the present invention, which constitutes an inverter chain circuit;
FIG. 4(B) is a sectional view taken along the line ■B--■B of FIG. 4(A), and FIG. 4(0) is a sectional view taken along the yc-ya line of FIG. 4(4). In addition, C! The illustration of the 0M0B inverters in the third and subsequent stages of the MOS inverter chain circuit is omitted.

The structure of this embodiment is that a semiconductor substrate (10a) is used instead of the conductive substrate (10a) in the second embodiment shown in FIG.
1)) and a high melting point metal film (190) formed thereon.
Since the configuration is similar to that of the first embodiment, this embodiment also has the same effects as the first embodiment shown in FIG.

Figure 5 (A) shows a thin [0M0 using MQS transistor]
The main part plan view of the thin film semiconductor element integrated circuit device according to the fourth embodiment of the present invention, which constitutes an S inverter circuit, is a cross section taken along the line VB-VB in FIG. 5(A). FIG. 5(0) is a sectional view taken along the line ya-ya in FIG. 5(A). Note that illustration of the CMOS inverters in the third and subsequent stages of the CMOS inverter chain circuit is omitted.

The structure of this embodiment is that a semiconductor substrate (LOA) is used instead of the conductive substrate (LOA) in the second embodiment shown in FIG.
b) and an n-type semiconductor film (181).

(1B2) l --- Replaced with high melting point metal film (191), (192),' --- which is the conductive film in this example.
Since the configuration is the same as that of the second embodiment except that -- is used, this embodiment also has the same effects as the first embodiment shown in FIG.

Note that up until now, CM
Although the description has been made by taking a thin film semiconductor element integrated circuit device that constitutes an OS inverter chain circuit as an example, the present invention is directed to an active layer that is to be at a predetermined common potential on a portion of the surface of an insulating film formed on the surface of a conductive substrate. The present invention can be generally applied to thin film semiconductor element integrated circuit devices in which an electric circuit is formed having a plurality of thin film semiconductor elements each having a region.

〔Effect of the invention〕

As described above, in the thin film semiconductor integrated circuit device of the present invention, a plurality of active regions having a common predetermined potential are formed on a portion of the surface of the insulating film formed on the surface of the conductive substrate. In a device in which an electric circuit is formed with thin film semiconductor elements as constituent elements, the active regions of these thin film semiconductor elements are each connected to a conductive substrate by a conductive film penetrating the insulating film. Since there is no need for a wiring film that commonly connects the active regions of the thin film semiconductor elements, the substrate area can be reduced and the wiring configuration can be simplified.

[Brief explanation of the drawing]

FIG. 1(A) is a plan view of essential parts showing an example of a conventional thin film semiconductor element integrated circuit device, and FIG. 1(B) is an I of FIG. 1(A).
A sectional view taken along the B-IB line, Figure 1 (0) is a sectional view taken along the 1O-Io line of Figure 1 (A), and Figure 2 (Shu is the clam 1 of this invention).
2 (CB) is a cross-sectional view taken along line IIB-[IB of FIG. 2 (A), and FIG. (A sectional view taken along the line 1ie-10 of Shu, FIG. 3(A) is a plan view of main parts showing a thin film semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. 3(B) is a cross-sectional view of a third Figure 3 (0) is a cross-sectional view taken along line B-[IB of Figure (A), Figure 3 (0) is a cross-sectional view taken along line 0-1ie of Shu, Figure 4 is FIG. 4(B) is a plan view of main parts showing the thin film semiconductor element integrated circuit device of Example 3.
Figure (A) is a cross-sectional view taken along line ■B-■B, @4 Figure (0) is a cross-sectional view taken along line ■0-■O of Figure 4 (Shu), and Figure 5 (A) is a cross-sectional view of the present invention. FIG. 5(B) is a plan view of main parts showing the thin film semiconductor element integrated circuit device of the fourth embodiment.
A cross-sectional view taken along the VB line, Figure 5 (C) is
It is a sectional view taken along the ya line. In the figure, α(j, (loa) and (lob)
are a conductive substrate, a conductive substrate and a semiconductor substrate, respectively.
The wire is an insulating film, and (S1a) and (32a) are n-MO8 of the 1st and 2nd stage 0M0S inverters, respectively.
n-type source region of T (active region to be at a common predetermined potential of multiple thin film semiconductor elements), (151) and (15
2) is a metal film (conductive film), (181) and (1B
2) is an n-type semiconductor film (a semiconductor of the same conductivity type as the active region of a thin film semiconductor element), and (190) is a high melting point interposed between the insulating film (a) and the semiconductor substrate (xob). The metal films (191) and (192) are high melting point metal films (conductive films). Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1114 Fig. 1 (E) 'H ¥ Agency Secretary Hannan 1. Indication of the case: Japanese Patent Application No. 59-056'751 2, Title of the invention: Thin film semiconductor integrated circuit device 3, Person making the amendment: Subject of the amendment 4: Column 6 for detailed description of the invention in the detailed description, Contents of pressure compensation (1) ) "Polycrystalline" is corrected to "polycrystalline layer" on page 6*'7 of the specification. that's all

Claims (1)

[Scope of Claims] (1) An electric device consisting of a plurality of thin film semiconductor elements each having an active region partially at a common predetermined potential on the surface of an insulating film formed on the surface of a conductive substrate. A thin film semiconductor device in which a circuit is formed, wherein the active regions of the plurality of thin film semiconductor devices are each connected to the conductive substrate by a conductive film penetrating the insulating film. Integrated circuit device. (2) The thin film semiconductor element integrated circuit device according to claim 1, wherein the conductive film is a metal film. (3) The conductive substrate is a conductive substrate, and the conductive film is a semiconductor film of the same conductivity type as the active region of the thin film semiconductor element. Thin film semiconductor element integrated circuit device. The thin film semiconductor device integration according to claim 1, wherein the conductive film is a semiconductor film of the same conductivity type as that of the active region of the thin film semiconductor device. circuit device. (5) The thin film semiconductor element integrated circuit device according to claim 1, wherein the conductive substrate is a semiconductor substrate and the conductive film is a high melting point metal film.