JPS60200632A - Code error detecting circuit - Google Patents

Abstract

PURPOSE:To execute easily a measurement even by a transmission line for one sequence data by sending both a pattern to be compared and a comparing pattern to a receiving side, and approviing an error rate, in a detecting circuit used for especially, a digital radio equipment. CONSTITUTION:In the transmitting side, as for a pseudo random code outputted from a pseudo random code generator 1 driven by a clock which has frequency- divided the output of a clock generator 11 into 1/2, a part of said code remain as it is, and the remaining part is converted to a series code by a parallel/series converting circuit 12 through an (n) bit delaying circuit 2 and sent out of a terminal 13. In the receiving side, a data and a clock are provided to a series/ parallel converting circuit 20 through a terminal 27 and 28. A seried data which is divided into clocks 73, 4 of two sequences by this circuit 20 and received is converted to parallel data 5, 6 of two sequences by using rise of this clock. This parallel data is provided to comparing circuits 23, 24 directly and through an (n) bit delaying circuit 21 and an (n-1) bit delaying circuit 22.

Description

DETAILED DESCRIPTION OF THE INVENTION (81) Technical Field of the Invention The present invention relates to a code error detection circuit, and more particularly to a code error detection circuit used in a digital radio device.

(bl) Prior Art and Problems A digital radio line usually has a protection line l for a working line n, and the error rate of the working line is constantly monitored, and if the error rate worsens, the line is switched to the protection line.

In this case, the number of data sequences differs depending on the modulation method,
For example, in the case of quadrature phase modulation, two series of data are required.

Fig. 1 is a diagram showing a conventional example of a code error detection circuit. Fig. 1 +al indicates a transmitting section, and Fig. 1 (bl indicates a receiving section. In Fig. 1, two series of data are input and output. Therefore, this is the case of four-phase phase modulation.

In the figure, 1 is a pseudorandom code generator, 2 and 5 are n-bit delay circuits, 6 is a comparison circuit, and 3, 4, and 7 to 9 are terminals, respectively.

The operation of the block connection diagram shown in FIG. 1+a+ is as follows.

The suspicious random code generated by the pseudorandom code generator 1 is branched into two. One part is directly connected to terminal 3, and the remaining part is delayed by n bits in n-bit delay circuit 2 and connected to terminal 4.
Two series of data, ie, data 1 and data 2, are respectively output.

In the receiving section shown in FIG. 1(b), an n-bit delay circuit 5 is inserted into the data 1 circuit so as to cancel out the delay time difference between data 1 and data 2 applied to terminals 7 and 8. Then, data 1 that has passed through the n-bit delay circuit becomes in phase with data 2.

Data 1 and 2 that are in phase are compared by a comparator 6 to check for errors.

When this code error detection circuit is applied to a single-series data transmission path, a parallel/serial conversion circuit (not shown) is required on the transmitting side to convert the output two-series data into one-series data, and a human-powered A serial/parallel conversion circuit (not shown) is required to convert 1 series data into 2 series data, but as described later, the clock distribution performed by the serial/parallel conversion circuit is always the same as the parallel/serial conversion on the transmitting side. Since the distribution is not always the same as that of the circuit, there is a problem that the output does not necessarily match the data on the transmitting side.

tel OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to provide a code error detection circuit that can be easily measured even on a series data transmission path.

fd+ Structure of the Invention The object of the invention is to provide a transmitting section that directly receives the output of a pseudo-random code generator, and the remaining section that includes a serial code generating means that generates a serial code in addition to a parallel/serial conversion circuit through a delay circuit. The receiving section includes a serial/parallel conversion circuit that converts the output of the serial code generating means into a parallel code, and a delay circuit provided on each output side of the serial/parallel conversion circuit to perform the serial/parallel conversion delayed by a delay circuit. the output part of the circuit,
a delay/comparison means for comparing the output portions of the serial/parallel conversion circuit that do not pass through the delay circuit; and a selection processing circuit for selecting and outputting an error-free output from among the outputs of the delay/comparison means. This is achieved by providing a code error detection circuit characterized by comprising:

Embodiment of the Invention FIG. 2 is a block connection diagram of an embodiment of the present invention.

In the figure, ■ indicates a pseudo-random code generator, 2 indicates an n-bit delay circuit, 10 indicates an A frequency divider, 11 indicates a clock generator, 12 indicates a parallel/serial conversion circuit, and 15 indicates a serial code generation means. , 20 is a serial/parallel conversion circuit, 21 is n-bi, I-
22 is an (n −1) bit delay circuit; 2 is a delay circuit;
3 and 24 are comparison circuits, 25 is a selection processing circuit, and 26
13, 14 and 27 to 29 respectively indicate delay/comparison means and terminals.

FIG. 3 is a time chart for explaining the operation of FIG. 2, and the numbers on the left side indicate the waveforms of the portions with the same numbers in FIG.

Therefore, the operation shown in FIG. 2 will be explained with reference to FIG.

First, the operation of ta+ in FIG. 2 is as follows.

The output of the clock generator 11 is divided into two parts, and one part is sent to the terminal 14.
Then, the remaining part is divided by two by the A frequency divider 10 and then applied to the pseudorandom code generator 1.

Therefore, m random codes driven by this clock are output from the code generator 1.

The outputted pseudorandom code is divided into two parts, one part is left as is, and the remaining part passes through the n-bit delay circuit 2, is converted into a serial code by the parallel/serial converter circuit 12, and is output from the terminal 13 together with the clock. Sent (Figure 3-■
and ■see).

Figure 2 (In the receiving section of bl, data and clock are connected to terminal 2.
7 and 28 to the serial/parallel converter circuit 20 (see FIG. 3 - ■ and ■).

The serial/parallel conversion circuit 20 divides the clock into two systems as shown in FIG.

Next, the received serial data is converted into parallel data of data a and data b using the rising edge of the clock shown in FIG.

Since this data is shifted by 4 bits from each other, Figure 3-■
When aligned using the falling edge of the clock shown in Figure 3-■
The parallel data shifted by 1 bit as shown in Figure 3 -
In-phase parallel data as shown in Figure-○ and [Phase] are connected in series/
It is obtained on the output side of the parallel conversion circuit 20.

For example, as shown in FIG. 3 - ■ and [Phase], when the data that matches the transmitter is obtained from the serial/parallel conversion circuit 20, there is no error pulse on the output side of the comparator circuit 20, so O is
An error pulse with an error rate of approximately 2 is obtained at the output of the comparator 24.

On the other hand, in cases not shown in Figure 3 =■ and ■, the delay circuit 22
As a result, the outputs of the error pulses of the comparison circuits 23 and 24 are reversed.

The selection processing circuit 25 compares the outputs from the comparison circuits 23 and 24 and outputs the one without an error pulse.

ffl As described in detail, according to the present invention, two patterns, the pattern to be compared and the pattern to be compared, are sent to the receiving side to test the error rate, so any pattern can be used. .

Further, since the circuit of the present invention does not have a negative feedback circuit, high-speed processing is possible up to the limit of the device.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a conventional example of a code error detection circuit, Fig. 2 is a block connection diagram showing an example of the present invention, and Fig. 3 is a diagram showing a conventional code error detection circuit.
Time charts are shown for explaining the operations in the figures. In the figure, 1 is a pseudo-random code generator, 2 and 21 are n
10 is a 2-frequency divider, 11 is a clock generator, 12 is a parallel/serial conversion circuit, 15 is a serial code generation means, 20 is a serial/parallel conversion circuit, 22 is n
-1 bit delay circuit, 23 and 24 are comparison circuits, 2
5 is a selection processing circuit, 26 is a delay/comparison means, 13.
14 and 27-29 indicate terminals, respectively.

Claims (1)

[Claims] The transmitting section is composed of a serial code generating means that directly sends a part of the output of the pseudorandom code generator, and the remaining part passes through a delay circuit to a parallel/serial converter circuit and generates a serial code, and the receiving section is a serial/parallel conversion circuit that converts the output of the serial code generating means into a parallel code, and an output portion of the serial/parallel conversion circuit delayed by a delay circuit provided on each output side of the serial/parallel conversion circuit. and an output portion of the serial/parallel conversion circuit that does not pass through the delay circuit, and a selection for selecting and outputting an error-free output from among the outputs of the delay and comparing means. 1. A code error detection circuit comprising a processing circuit.