JPS60201380A - Luminous display - Google Patents
Luminous displayInfo
- Publication number
- JPS60201380A JPS60201380A JP59058862A JP5886284A JPS60201380A JP S60201380 A JPS60201380 A JP S60201380A JP 59058862 A JP59058862 A JP 59058862A JP 5886284 A JP5886284 A JP 5886284A JP S60201380 A JPS60201380 A JP S60201380A
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting element
- light
- layer
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 description 23
- 239000000758 substrate Substances 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Led Devices (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、電流制限回路を内蔵したモノリシック形の発
光表示装置に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a monolithic light emitting display device having a built-in current limiting circuit.
（ロ）従来技術
従来、単一基板に複数の発光素子を配置形成したモノリ
シック形の発光表示装置を駆動する場合、各発光素子の
過電流破壊を防止するために外部駆動回路に電流制限抵
抗を外付けしている。(B) Prior Art Conventionally, when driving a monolithic light emitting display device in which multiple light emitting elements are arranged and formed on a single substrate, a current limiting resistor is installed in the external drive circuit to prevent overcurrent damage to each light emitting element. It is attached externally.
このため、モノリシック形の発光表示装置自体の小型化
を図っても電流制限抵抗を内蔵してないので、外部駆動
回路に電流制限抵抗を外付けしなｔすればならない。即
ち、実装面積が比較的大きなものになり、実装作業に手
間がかかるという欠点がある。For this reason, even if the monolithic light emitting display device itself is miniaturized, it does not have a built-in current limiting resistor, so it is necessary to externally attach a current limiting resistor to an external drive circuit. That is, there is a drawback that the mounting area is relatively large and the mounting work is time-consuming.
これらの原因により、本装置が実装される機器の小型化
を図るのが回能である。Due to these reasons, it is important to downsize the equipment in which this device is mounted.
（ハ）目的
本発明は、発光表示装置の外部駆動回路の実装面積を小
さくし、且つ、実装作業の容易である発光表示装置を提
供することを目的としている。(C) Objective The object of the present invention is to provide a light emitting display device in which the mounting area of an external drive circuit of the light emitting display device can be reduced and mounting work is easy.
（ニ）構成
本発明に係る発光表示装置は、マトリクス状に配列され
た各発光素子のうち、各判御配列される発光素子を接続
する上部電極と、各行に配列される各発光素子の共通電
極としての下部電極とを具備したモノリシック形の発光
表示装置であって、前記上部電極と下部電極との間で、
且つ、前記発光素子と直列に抵抗層を介在したことを特
徴とする。(D) Structure The light emitting display device according to the present invention has an upper electrode that connects the light emitting elements arranged in a matrix among the light emitting elements arranged in a matrix, and a common electrode between the light emitting elements arranged in each row. A monolithic light emitting display device comprising a lower electrode as an electrode, wherein between the upper electrode and the lower electrode,
Further, a resistive layer is interposed in series with the light emitting element.
（ボ）実施例 第１図は本発明の一実施例を略示した斜視図である。(B) Example FIG. 1 is a perspective view schematically showing an embodiment of the present invention.
ｌＯは、例えばＧａＡｓからなる半絶縁基板であり、２
０は、前記半絶縁基板ｌＯの表面に形成するＮ層層から
なる帯状の下部電極であり、各行ごとに配列された各発
光素子４０の共通電極である。lO is a semi-insulating substrate made of GaAs, for example, and 2
0 is a band-shaped lower electrode made of an N layer formed on the surface of the semi-insulating substrate IO, and is a common electrode of each light emitting element 40 arranged in each row.
３０は、キャリア濃度の小さい比抵抗の大きいＮ一層か
らなる抵抗層であり、前記下部電極３０と後述する各発
光素子４０との間にそれぞれ比較的厚く形成されている
。Reference numeral 30 denotes a resistance layer made of a single layer of N having a low carrier concentration and a high resistivity, and is formed relatively thickly between the lower electrode 30 and each light emitting element 40, which will be described later.
４０は、２層４１ ＮＮ４２から構成される発光素子で
あり、それぞれマトリクス状に配列されている。40 is a light emitting element composed of two layers 41 and NN42, each of which is arranged in a matrix.
この発光素子４０は前記抵抗層３０の表面にＮ層４２を
その上部に２層４１が形成されている。This light emitting element 40 has an N layer 42 formed on the surface of the resistive layer 30, and two layers 41 formed thereon.
５０ば、各列ごとに配列された各発光素子４０のコンタ
クト層４３に接続されるＡｌ或いは篩等からなる上部電
極である。50 is an upper electrode made of Al or a sieve, which is connected to the contact layer 43 of each light emitting element 40 arranged in each column.
次に、上述した実施例に係る発光表示装置の製造工程を
説明する。Next, the manufacturing process of the light emitting display device according to the above-described embodiment will be explained.
■ 半絶縁基板ｌＯの表面にＮ”−ＧａＡｓをエピタキ
シャル成長させることにより、下部電極２０を形成する
。(2) A lower electrode 20 is formed by epitaxially growing N''-GaAs on the surface of the semi-insulating substrate IO.
■ 前記下部電極２０の表面にＮ”−−ＧａＡｓを所望
の膜厚でエピタキシャル成長させることにより、抵抗ｍ
ａｏを形成する。(2) By epitaxially growing N''--GaAs to a desired thickness on the surface of the lower electrode 20, the resistance m is increased.
form ao.
■ 前記抵抗層３０の表面にＮ−ＧａＡｌＡｓをエピタ
キシャル成長させることによりＮ層４２を形成する。(2) An N layer 42 is formed on the surface of the resistance layer 30 by epitaxially growing N-GaAlAs.
■ 前記Ｎ層４２の表面にＰ−ＧａＡＩＡｓをエピタキ
シャル成長させることにより、ＰＩｉｉ４１を形成する
。(2) PIii 41 is formed by epitaxially growing P-GaAIAs on the surface of the N layer 42;
■ 前記Ｐｍ４１０表面にＰ”−ＧａＡｓをエピタキシ
ャル成長させて、コンタクト層４３を形成する。(2) A contact layer 43 is formed by epitaxially growing P''-GaAs on the surface of the Pm410.
尚■〜■までの成長工程は、所謂ＭＢＥ装置でもって、
順次厚さ方向に制御され連続成長させている。The growth steps from ■ to ■ are performed using a so-called MBE device.
Growth is controlled sequentially and continuously in the thickness direction.
■ 半絶縁基板ｌＯまで届くメサエッチングを施して各
行ごとに下部電極２０を絶縁分離させる。(2) Perform mesa etching that reaches up to the semi-insulating substrate IO to insulate and separate the lower electrodes 20 for each row.
■ 下部電極２０まで届くように前記下部電極２０と直
交する方向でメサエッチングを施して、各列ごとの各発
光素子４０や各抵抗１舗３０をそれぞれ絶縁分離さ一仕
る。(2) Mesa etching is performed in a direction perpendicular to the lower electrode 20 so as to reach the lower electrode 20, thereby insulating and separating each light emitting element 40 and each resistor 30 in each row.
■ 各列ごとのコンタクト層４３に上部電極５０を蒸着
形成してパターニングした後、不要な前記コンタクト層
４３を除去する。(2) After forming the upper electrode 50 on the contact layer 43 of each column by vapor deposition and patterning, unnecessary contact layer 43 is removed.
面、説明の都合上、第１図には、上部電極５０による２
層４１とＮＩＥｉ４２との短絡防止するための絶縁層を
示していない。For convenience of explanation, FIG.
An insulating layer for preventing short circuit between layer 41 and NIEi 42 is not shown.
前記抵抗層３０はＭＢＥ装置でもって、他の各層と連続
してエピタキシャル成長されるので、その製造が容易に
なるという効果を奏する。Since the resistive layer 30 is epitaxially grown successively with other layers using an MBE apparatus, it has the advantage of being easy to manufacture.
面、上述の実施例で、ｐｌ＊４ｉとＮ層４２とで構成し
た発光素子４０を１９１１にとって説明しているが本発
明はこれに限定されないことは勿論である。In the above-mentioned embodiment, the light emitting element 40 composed of pl*4i and the N layer 42 is explained using 1911, but the present invention is of course not limited to this.
また、抵抗層３０を下部電極２０と発光素子４０との間
に介在させた場合を説明しているが１１本発明番よこれ
に限定されず、発光素子４０と上部電極５０との間に介
在させてもよい。In addition, although a case has been described in which the resistance layer 30 is interposed between the lower electrode 20 and the light emitting element 40, the present invention is not limited to this, and the resistance layer 30 is interposed between the light emitting element 40 and the upper electrode 50. You may let them.
（へ）効果
本発明に係る発光表示装置は、各発光素子と直列に抵抗
層を介在させ、電流制限抵抗を発光素子と同一チップ内
に形成しているので、電流制限抵抗を外部駆動回路に外
付けする必要がなし）。(F) Effect The light-emitting display device according to the present invention has a resistance layer interposed in series with each light-emitting element, and the current-limiting resistor is formed in the same chip as the light-emitting element, so the current-limiting resistor is connected to the external drive circuit. (no external connection required).
従つて、本発明によれば実装面積を小さくし、実装作業
が容易にできる。Therefore, according to the present invention, the mounting area can be reduced and the mounting work can be facilitated.
第１図は本発明の一実施例を略示した斜視図である。
２０・・・下部電極、３０・・・抵抗層、４０・・・発
光素子、５０・・・上部電極。
特許出願人 ローム株式会社
代理人 弁理士 大 西 孝 治FIG. 1 is a perspective view schematically showing an embodiment of the present invention. 20... Lower electrode, 30... Resistance layer, 40... Light emitting element, 50... Upper electrode. Patent Applicant: ROHM Co., Ltd. Agent, Patent Attorney: Takaharu Ohnishi
Claims (2)
素子を接続する上部電極と、各行に配列される各発光素
子の共通電極としての下部電極とを具備したモノリシッ
ク形の発光表示装置において、前記上部電極と下部電極
との間で、且つ、前記発光素子と直列に抵抗層を介在し
たことを特徴とする発光表示装置。(1) A monolithic light-emitting display in which a plurality of light-emitting elements are arranged and formed on a single substrate, and includes an upper electrode that connects each light-emitting element, and a lower electrode that serves as a common electrode for each light-emitting element arranged in each row. A light emitting display device, characterized in that a resistive layer is interposed between the upper electrode and the lower electrode and in series with the light emitting element.
あることを特徴とする特許請求の範囲第１項記載の発光
表示装置。(2) The light emitting display device according to claim 1, wherein the resistance layer is epitaxially grown.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59058862A JPS60201380A (en) | 1984-03-26 | 1984-03-26 | Luminous display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59058862A JPS60201380A (en) | 1984-03-26 | 1984-03-26 | Luminous display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60201380A true JPS60201380A (en) | 1985-10-11 |
Family
ID=13096524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59058862A Pending JPS60201380A (en) | 1984-03-26 | 1984-03-26 | Luminous display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60201380A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8089078B2 (en) | 2008-03-28 | 2012-01-03 | Sanken Electric Co., Ltd. | Light emitting device |
| JP2015026731A (en) * | 2013-07-26 | 2015-02-05 | 学校法人 名城大学 | Semiconductor optical element array, manufacturing method thereof, and display device using semiconductor optical element array |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5017777A (en) * | 1973-05-11 | 1975-02-25 | ||
| JPS58170058A (en) * | 1982-03-31 | 1983-10-06 | Fujitsu Ltd | Photointegrated semiconductor device |
-
1984
- 1984-03-26 JP JP59058862A patent/JPS60201380A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5017777A (en) * | 1973-05-11 | 1975-02-25 | ||
| JPS58170058A (en) * | 1982-03-31 | 1983-10-06 | Fujitsu Ltd | Photointegrated semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8089078B2 (en) | 2008-03-28 | 2012-01-03 | Sanken Electric Co., Ltd. | Light emitting device |
| JP2015026731A (en) * | 2013-07-26 | 2015-02-05 | 学校法人 名城大学 | Semiconductor optical element array, manufacturing method thereof, and display device using semiconductor optical element array |
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