JPS60201445A - Multiple interruption processing device - Google Patents

Abstract

PURPOSE:To improve immediately executing property for an interruption which requires an urgency, by providing a register for identitying the degree of priority of a processing program which is being executed at present. CONSTITUTION:If an interrupting signal INT1 of a high-order rank is generated when an interruption whose degree of priority is low is being processed, the output of an AND circuit 14-1 goes to ''1'' and it is inputted to an interruption processing controlling circuit (ICONT circuit) 13 and a transfer gate 18 and 19. An IST register 11 saves a code 01B for indicating a fact that the interruption of a low-order is being processed, in a stack register 12, and resets newly a code 10B for indicating a fact that an interruption of a high-order is being processed. Even if an interrupting signal of a low-order is inputted when an interruption be being processed. Even if an interrupting signal of a low-order is inputted when an interruption is being processed, the output of an AND circuit 14 goes to ''0'' and the interruption processing is not executed because ''0'' is outputted through an invertor 16.

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to a multiplex interrupt processing device, and in particular, a multiplex interrupt processing device that can instantly perform multiple It relates to an interrupt processing device that executes interrupt processing.

(Prior art) Many microcontrollers have various built-in interrupt processing functions. It has a great function.

In the future, as the performance of microcomputers improves, control by the microcomputer will become more complex, and the interrupt function will also require immediate start of interrupt processing, more flexibility in positioning the destination after 9 interrupts, and an increase in the number of interrupts. is required.

Conventionally, in microcontrollers that have such a built-in interrupt function, when a predetermined interrupt process is executed, the master interrupt operator flag, which instructs all interrupt reception to be enabled or disabled, is automatically set to mode.

Therefore, if the program must be processed by other high-priority multiple interrupts during a specified interrupt, execute the instruction to set this master interrupt enable flag to enable mode, and then Waits for high-level interrupt requests. However, in this case, the master interrupt permission flag allows acceptance of all interrupts, and lower priority interrupts may also be processed, so the master interrupt permission flag is set to permission mode. Other interrupts with lower priority are interrupt r! for individual interrupts. The individual permission flag indicating town f or prohibition kn must be set to northern prefecture mode by a predetermined command. Further, at the time when a predetermined interrupt ends, it is necessary to set the individual permission flags for other low-priority interrupts again in the association permission mode. Therefore, in a conventional microcontroller that handles such an interrupt function, if an urgent interrupt request occurs (for example, when the entire control system of the microcontroller is powered down), the master interrupt permission flag and priority level are @1. There are drawbacks such as the inability to execute program processing immediately due to interrupts that contribute to
Furthermore, each interrupt permission flag 'e! The problem is that the program processing unit must be operated by predetermined commands, and the limited program area cannot be used effectively.

(Object of the Invention) The object of the present invention is to eliminate the drawbacks of conventional multiple interrupt processing devices, and to be able to immediately start program processing necessary for more urgent interrupts. Furthermore, it is an object of the present invention to provide a high-performance multi-current interrupt processing device that does not require repeated execution of a predetermined command related to interrupt processing and can use the program area for the original control purpose for ringing. .

(Rinse of the Invention) According to the present invention, in multi-current interrupt processing that executes interrupt processing based on interrupt priority, program address save/restore control and branch address an interrupt processing means for generating a predetermined interrupt; a storage means for recording a quality judgment value corresponding to a priority of a predetermined interrupt according to instructions from the interrupt processing means; a side angle for controlling the saving of the degree identification value and a return to the storage means, or a permission means for controlling the suspension, when executing an interrupt process for an interrupt permitted by the permission means;
The contents of the storage means are saved, and the 7'c & priority identification value corresponding to the interrupt is set in the storage means, and when the first interrupt processing is completed, the contents are saved and fcf! There is obtained a multiple interrupt processing device characterized in that the previous identification value is restored to the storage means.

(Real axis example) Next, an example of an uninvented real axis will be described with reference to the drawings.

5- The drawing shows an embodiment of the invention. In the figure, the non-implemented example is a multi-power interrupt processing device that executes interrupt processing based on interrupt priority, and saves and restores program addresses and generates branch addresses in conjunction with execution of interrupt processing. an interrupt processing means 13; a storage means 11 for storing an fc priority identification value corresponding to the priority of a predetermined interrupt according to instructions from the interrupt processing means; A control means 12 that fully controls the saving of the identification value and its restoration to the storage means, and a permission means 14 that controls permission or suspension of interrupt processing execution based on the contents of the previous storage means.
including.

The storage means 11 stores whether, at any given time, the microcomputer (not shown) is executing an interrupt processing program with a high priority or an interrupt processing program with a low priority; The flag is a 2-bit, 9-bit interrupt priority status identification register that stores the status of either interrupt processing or not. This is a stack register that saves and stores the contents of the destination state identification register 11 and restores the stored contents to the post-interrupt state identification register 11 when the interrupt processing is completed. The interrupt processing means 13 saves the contents of the post-interrupt state identification register 11 to the t-stack register 12,
and a control signal P for saving the current contents of the nologram counter to the data memory or dedicated stack register.
This is an interrupt processing control circuit that generates C8T and generates a start address of an interrupt processing program according to an interrupt signal.

The enabling means 14 includes a two-man power AND circuit 14-1 and a three-man power ANI (ANI) circuit 14-2 to l4-nf, and further includes an inverter which outputs the upper 1 bit of the 2 bits of the interrupt priority state identification register 1. 15, and an inverter 16 whose input is the output of the lower l bits.

(n-1) The input OR circuit 17 has the AND@ path 14-
It is an OR circuit that takes all outputs from 2 to 14-n as input.

transfer group) 18 and 19 are the AND1g
When the output of the l path 14-1 is a logical value 11'', the logical value uO is set in the upper bit of the interrupt priority identification register 11, respectively.
” (GND level) to the lower bit, transfer gate 2 is set.
o and 21, the output of the IQi2OR circuit 17 is ul'''
This is a transfer gate for setting the upper bit of the interrupt priority status identification register 11 to the lower bit of tfQIji when .

Note that among the n types of interrupt signals lNTl to INTn,
It is assumed that the interrupt signal lNTl has a high interrupt priority, and the interrupt signals INT2 to INTn are uniformly low priority interrupts.

Next, the operation of one embodiment of the present invention will be explained in more detail.

By sending a reset signal to the microcomputer, the contents of the interrupt destination state identification register (hereinafter referred to as the IST register) 11 are code 0OB, which indicates that no interrupt processing is being performed.
(binary number) is set.

In this state, the low priority interrupt signals INT2~
Any interrupt of INT n, for example interrupt signal I
If NT 2 occurs, AND [g1 road 14
The input from the interrupt signal INT2 of -2 is 11e, and the output 00B of the I8T register 11 is inverted by the inverters 15 and 16, and the input from the inverters 15 and 16 of the AND circuit 14-2 is also ole. Because there is, u
l” is output and the interrupt processing control (b) path (hereinafter IC0N
(referred to as T circuit) 13 and (JR circuit 17).

The ICoNT circuit 13 uses the output ul'' from the AND circuit 14-2 to start an interrupt processing program corresponding to the interrupt of the interrupt signal INT2.
1'' The contents of the register 11 are saved to the stack register 12, and the save control signal PC8Ti is outputted to save the contents of the current nologogram counter.

The IST register 11 transfers the interrupt status code 008'ft to the stack register 12 in response to the input of the control signal PCB'l'. Then, the code OIB inputted to the output ole of the zero circuit 17 through the transfer gates 2o and 21 is newly stored in the If9T9 register 11.

The ICoNT circuit 13 outputs the control signal PC8T, and also generates an interrupt processing program start address corresponding to the interrupt signal INT2, and sets it in the program counter. The circuit 13 starts all predetermined processing (interrupt processing) from the program address where the circuit 13 generated it. Even if any one of the interrupt signals INT2 to INTn newly occurs during the interrupt processing, the lower bit output "l" of the I8T register 11 causes the ANj) circuit 1 to be output via the inverter 16.
Since the input of 4-2 to 14-n is aO'', the output is @θ
'', and the interrupt signal is not input to the ICoNT circuit 13.

That is, even if an interrupt of the same level occurs during interrupt processing of a lower priority, it will not be accepted and the interrupt will be put on hold. - If the high-level interrupt signal lNTl is generated during the low-level interrupt processing, the interrupt signal lNTl of the AND circuit 14-1
The input by ``l'' is huge.

The upper bit of I8T register 11 is set to 1 due to the output “0”.
〇- The input via the inverter IFI is 11″, so the AN
Dlpl path 14-1 + D output U"l" and 7, ICo
The signal is input to the NT circuit 13 and transfer gates 18 and 19. The IC0N'l'' circuit 13 outputs the save control signal PC8'l' to the LST register 11 and the stack register 12 in the same way as when the interrupt signal INT2 was interrupted, and thereby the 18T register 11 outputs a low-level interrupt. The code OIB indicating that processing is in progress is saved to the stack register 12, and at the same time the @ in the current program counter is saved, and the message is communicated to transfer cards 18 and 19' to indicate that a high-level interrupt is being processed. A code IOB indicating that an interrupt is being processed is newly set in the stack register 12. This causes the stack register 12 to stack the previous code OOB that indicates that an interrupt is not being processed and the previous code 1) IB that indicates that an interrupt is being processed. Thereafter, the ICONTIg path 13 generates a start point for the interrupt processing of the interrupt signal lNTi, so that the CPU executes the predetermined interrupt processing clock 2m?
Start. During interrupt processing of interrupt current signal INT l, Is
Due to the output ulo of the upper bit of the T register 11, the input to the AND circuit 14-1-14-n via the inverter 15' becomes uO'', so the interrupt signals lNT1 to IN
Even if a new Tn interrupt occurs, none of them are executed and are suspended.

When the interrupt of the interrupt signal lNTl is completed, the interrupt end signal EOI from the CPU is input to the lST register 11 and xp look register 1, and the code olB of the IST register 11 stacked last in the stack register: jl12.
returns to the IST register ii, and at the same time the interrupt signal lN
The contents of the 10-gram program counter are also saved from the stack for saving the program counter, so the interrupt processing of the interrupt signal INT2 is restarted. do.

Further, when a high-level interrupt I8@INT occurs, the interrupt processing for interrupt No. 18 1NTl is started in the same manner as described above, and low-level interrupt signals INT2 to 1NTn are not accepted and are held on hold.

When the interrupt signal INT2 is completed, the EOI bond signal from the CPU is output as the interrupt signal IN in the same manner as described above.
The code OOB of the IST register 11 saved in the stack register 12 immediately before the interrupt processing of 'J'2 returns to 18TL/J111Vc, and the process returns to the norogram processing before the interrupt processing of the interrupt signal INT2.

Thereafter, each time an interrupt occurs, the same control as described above is performed. Note that the stack register 1 explained in this embodiment
2 may be either a dedicated register or a data memory stack (the contents of the LET register 11vP'E can be saved at the same time as the contents of the grogram counter by adding it to the grogram counter, etc.).

In this embodiment, the interrupt priority is explained as having two levels, high and low, but in the case of multi-bundle interrupt processing with two or more levels of priority depending on the number of interrupts, 4. By increasing the bit length r of the I8'l' register and the stack register, a register is provided to identify the priority of the similar multi-current interrupt processing 10 grams. 13- Multi-page interrupts with priority are controlled by dynamically determining whether to execute or suspend them, and the contents of the interrupt priority pupil register are automatically saved and restored at the start and end of interrupt processing. In processing, there is no need to manipulate individual permission flags for low-priority interrupts in the processing program, making them urgent?
! - It is excellent in immediate execution of dormitory interruptions, and has the effect of being able to effectively utilize the 10 Durham area money for the original control purpose.

[Brief explanation of drawings]

The drawing shows a multiple interrupt processing system according to an embodiment of the present invention. 11... Interrupt priority state identification register, 12...
...Stack register, 13...Interrupt processing control circuit. 14 1=14-n=--kNl) circuit, l 5.
l 6・−・−・Inverter, 17・・・・・・oit
Circuits, 18, 19, 20. 21...Transfer Kate. 14-

Claims (1)

[Claims] In a multiple interrupt processing device that executes interrupt processing based on interrupt priority, an interrupt processing that saves and restores a program address and generates a branch address as the interrupt processing is executed. storage means for storing a priority identification value corresponding to the priority of a predetermined interrupt according to an instruction from the interrupt processing means; a control means for controlling return NI to the memory means; and the IU2.
A permission means for permitting or suspending execution of interrupt processing based on the contents of the storage means? I-In cooperation, when executing the interrupt processing for the avoidable interrupt, save the contents of the above-mentioned means 1, and set the following *mt separate value kffl corresponding to the interruption. tie
@r: A multiple interrupt processing device in which the priority identification value is set in the rumor means, and when the interrupt processing is completed, the saved priority identification value is returned to the storage means.