JPS60201715A - Ccd delay circuit - Google Patents

Abstract

PURPOSE:To synthesize the outputs of two CCD delay circuits which are driven alternately with no distortion by connecting the collectors of two differential circuits in an X shape and controlling the current sources of both differential circuits with outputs of both delay circuits. CONSTITUTION:Both CCD delay circuits 12A and 12B are connected in parallel in order to attain a sampling speed higher than the working limit level of CCD. Then both circuits 12A and 12B are driven alternately by clocks CK and the inverse of CK to attain apparently a double sampling speed. The outputs of both delay circuits are synthesized by switching a switch circuit 19 with both clocks CK and the inverse of CK. The circuit 19 consists of two differential circuits (30, 31, 41) and (32, 33, 44) with collectors connected in an X shape. Both differential circuits are driven alternately with clocks and therefore the outputs of both CCD delay circuits supplied to terminals 42 and 45 are synthesized and delivered to an output terminal 40.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a CCD delay circuit used, for example, in a TBC (time base correction circuit) regarding a reproduction signal of a video disc.

"Background Art and its Problems" For example, a CCD (charge coupled device) is used as an analog variable delay circuit of a TBC (time base correction circuit) of a video disc playback circuit. FIG. 1 shows an example of a TBC using this CCD.

In Fig. 1, 1 indicates the input terminal, and the reproduced color video signal from the video disc is transferred from the input terminal 1 to the CCD 2.
At the same time, the synchronization signal in this color video signal is supplied to the synchronization signal separation circuit 3, and the separated horizontal synchronization signal is supplied to the phase comparison circuit 4. Phase comparison circuit 4
A reference horizontal synchronization signal is supplied from the reference signal generation circuit 5, and the phase of the reproduced horizontal synchronization signal output from the synchronization signal separation circuit 3 and the phase of the reference synchronization signal output from the reference signal generation circuit 5 are compared. , the comparison output of the phase comparison circuit 4 is supplied to the addition circuit 6. A sampling clock is supplied from the clock generation circuit 10 to the CCD 2, and the CCD
The output of D2 is taken out to the output terminal T, and the burst signal being outputted is separated by the burst gate circuit 8 and supplied to the phase comparator circuit 9.

The phase comparator circuit 9 is supplied with a continuous wave of 3.58 MHz (NTSC system) output from the reference signal generation circuit 5, and is connected to the burst signal output from the burst gate 8 and the continuous wave output from the reference signal generation circuit 5. waves are compared,
The output of the phase comparator circuit 9 is supplied to the adder circuit 6. The output of adder circuit 6 is supplied to clock generation circuit 10. The clock generation circuit 10 has a configuration of a VCO (voltage controlled oscillator) whose oscillation period is linearly controlled by a control voltage, for example, and the clock generation circuit 10 is configured by the output of the adder circuit 6.
The period of the output is controlled, and this output is supplied to the CCD 2 as a sampling clock.

The TBC circuit described above compares the phase of the horizontal synchronization signal supplied to the phase comparison circuit 4 via the synchronization signal separation circuit 3 and the phase of the reference synchronization signal supplied to the phase comparison circuit 4 from the reference signal generation circuit 5. A loop that calculates the correction amount and changes the delay amount of the CCD 2 according to this correction amount, and a phase comparison between the phase of the parsed signal supplied to the phase comparison circuit 9 via the burst gate 8 and the phase of the reference signal generation circuit 5. It is constituted by a loop that compares the phase ratio of the reference signal supplied to the circuit 9 to determine the amount of correction, and changes the amount of delay of the CCD 2 in accordance with this amount of correction. By using a loop that compensates for the jitter component using the phase of the synchronization signal, the jitter component included in the color video signal is removed until it becomes approximately 1/10, and the jitter component is compensated for by the phase of the nost signal. A feedback loop that compensates for the jitter component is removed until the jitter component is within a few microseconds.

A video signal output from a video disc usually contains a jitter component of about 10 μsec, and in the worst case, a jitter component of 30 μsec. Therefore, the TBC of this video disc playback circuit is 30μ.
It must be able to compensate for the jitter component of sec. Therefore, as shown in FIG.
The center delay time DLm i d of the delay time of 2 is 70 μs.
ec, the delay time of CCD 2 to compensate for this 30μsec jitter component is the maximum delay time DL
The maximum delay time is 85 μsec, and the minimum delay time DLmin is 55 μsec.

The delay time DL of CCD 2 depends on the number of stages of CCD and CC
It is determined by the period Ts of the timing clock supplied to D, and is expressed as DL=TSXK...■.

Therefore, for example, when a 680-stage COD is used as the CCD 2, the sanding period TSI when the maximum delay time DLmax is given by the formula (■) is Ts, = 85 x - drunkenness =
The sampling frequency fsl at this time is fsl-0,125-8M[-1z.

Also, the sampling period TS2 when the minimum delay time DLmin is TS2-55 x Ti = 0.08μsec from the formula (■),
The sampling frequency 152 at this time is fSz=-knee=12.51viHz0.08. Therefore, the sampling frequency fs supplied to the CCD 2 is 81 ViHz ~ 12.5 MH2
It becomes a clock with a frequency in the range of .

However, the frequency fS is 8 MHz to 12 MHz.
, 5 MHz, the sampling frequency is too low to sample the video signal, which causes the problem of aliasing distortion.

Therefore, for example, it is conceivable to connect two 680-stage CCDs in cascade as a variable delay circuit to configure a TBC circuit as a 1360-stage COD. However, if the sampling clock at this time is similarly calculated from equation (2), the sampling frequency fS becomes fs = 16M) (z ~ 25MH2), and the clock frequency at the limit of the operating speed of the COD, for example, 15
The frequency exceeds MHz and CCD2 does not operate.

Therefore, by connecting 680 stages of CODs in parallel as a variable delay circuit and driving these CODs in parallel, the sampling frequency does not fall within the video signal band and the CC
A TBC circuit can be constructed that can sample a video signal at a sampling frequency that does not exceed the operating limit of D and can compensate for a 30 μsec jitter component. However, by connecting CCDs in parallel like this, the C
When driving CDs in parallel, CCDs connected in parallel
The switch circuit that synthesizes the respective outputs of the two must be capable of high-speed operation and must have a configuration that does not distort the analog waveform.

``Object of the Invention'' Accordingly, an object of the present invention is to provide a CC switch circuit which operates at high speed and has a configuration that does not distort the analog waveform, and which is capable of sufficiently compensating for the jitter component of a video disc.
An object of the present invention is to provide a D delay circuit.

"Summary of the Invention" This invention controls first and second CCDs having a common input signal with clocks having the same frequency and opposite phases to each other, and and a second CCD
In a CCD delay circuit in which the output of each of the six circuits is selected and taken out by a switch circuit controlled by a clock, the collectors are cross-connected to each other, and a signal current source is connected to each of the six emitter connection points. It has first and second differential circuits, and has respective signal current sources connected to the first and second CCs.
D, supplies the above clock to the first and second differential circuits, causes the first and second differential circuits to perform switching operations, and obtains a selected output from at least one collector connection point. This is a CCD delay circuit designed as follows.

"Embodiment" An embodiment of the present invention will be described below with reference to the drawings. In FIG. 3, reference numeral 11 indicates an input terminal, and the color video signal is transmitted from the input terminal 11 to the CCD 12A,
The horizontal synchronizing signal is supplied to the CCD 12 B and also to the synchronizing signal separation circuit 13 , and the separated horizontal synchronizing signal is supplied to the phase comparator circuit 14 . This color video signal is obtained by, for example, irradiating a laser beam onto an optical disk on which the video signal is FM modulated and recorded, and then performing FM demodulation. , for example, contains a jitter component of up to 30 psee.

A reference signal is supplied from the reference signal generation circuit 15 to the phase comparison circuit 14, and the phase of the horizontal synchronization signal output from the synchronization signal separation circuit 13 and the phase of the reference synchronization signal supplied from the reference signal generation circuit 15 are compared. The phase comparison output is supplied to the adder circuit 16.

CCD-12A and CCD i 2.13 are supplied with clocks CK and CK having opposite phases and the same frequency from the clock generation circuit 17.
The 2B sampling output is supplied to the switch circuit 19. The switch circuit 19 is supplied with the clock CK and the clock -d from the clock generation circuit 11, and the clocks CK and CK? The output of CCD 12A and the output of CCD 12B are switched, and the output terminal 2
At the same time, the output of one CCD is taken out at 0, and the output of the switch circuit 19 is supplied to the phase comparator circuit 22 via the burst gate 21.

A reference signal is supplied from the reference signal generation circuit 15 to the phase comparison circuit 22, and the phase of the burst signal outputted from the burst gate 21 and the phase of the continuous wave outputted from the reference signal generation circuit 15 are compared, and a phase comparison is performed. Output is adder circuit 1
6.

The output of the adder circuit 16 is supplied to a clock generation circuit 17. The clock generation circuit 11 is, for example, a VCO (voltage controlled oscillator), and the period of the output of the clock generation circuit 17 is linearly controlled by the output of the adder circuit 16, and this output is used as the sunnoring clock CK and the CCP 12.
A and CCD 1.2 are supplied to B.

This TBC circuit compares the phase of the horizontal synchronization signal supplied to the phase comparison circuit 14 via the synchronization signal separation circuit 13 and the phase of the reference signal supplied to the phase comparison circuit 14 from the reference signal generation circuit 15. A loop that determines the correction amount and changes the delay amount of the CCDs 12A and 12B according to this correction amount, and a loop that calculates the phase of the pulse signal supplied to the phase comparison circuit 22 via the burst gate 21 and the phase from the reference signal generation circuit 15. The correction amount is determined by comparing the phase ratio of the continuous wave supplied to the comparator circuit 22, and the CCD is adjusted according to this correction amount.
12A and a loop that changes the delay amount of 12B. A loop that compensates jitter components based on the phase of the synchronization signal removes the jitter components until the jitter components included in the color video signal becomes approximately 1/10, and a loop that compensates jitter components based on the phase of the burst signal. The jitter component is removed by Dovano Clouzot until the jitter component is within a range of several p sec.

As mentioned above, the video signal output from the video disc usually contains a jitter component of about 10 μsec, and in the worst case, a jitter component of 30 μsec. For example, a 680-stage CCD as a variable delay circuit.
If a TBC circuit is configured with one TBC circuit, the clock frequency for obtaining the above-mentioned amount of delay required for jitter absorption becomes too low for sampling the video band. Furthermore, if a TBC circuit is constructed by cascading two CODs each having 680 stages as a variable delay circuit, for example, the sampling frequency will exceed the operating limit of the CCD and the TBC circuit will not operate. Therefore,
A TBC circuit according to an embodiment of the present invention has a configuration in which, for example, two 680-stage CCDs are connected in parallel as variable delay elements, and the two CCDs are driven in parallel. Therefore, a TBC circuit can be constructed in which the sampling frequency Ts is a frequency at which the video signal band can be sampled, the video signal can be sampled at a sampling frequency that does not exceed the operating limit of the CCD, and the 30 μsec jitter component can be compensated for.

That is, the input signal shown in FIG. 4A is sampled as shown in FIG. 4B by the clock CK shown in FIG. 4E, and outputted from the CCD 12A. The input signal shown in FIG. 4A is sampled as shown in FIG. 4C by the clock CK shown in FIG. 4F, and outputted from the CCD 12B. The output shown in FIG. 4B, which is clocked by the clock CK, and the output shown in FIG. 4C, which is clocked by the clock CK, are alternately selected by the switch circuit 19 controlled by the clock CK. A sampled output is obtained at output terminal 20 as shown. This is equivalent to sampling the input signal shown in FIG. 4A at a frequency twice the frequency of the clock CK. Therefore, CCD12A.

The clock frequency supplied to CCD 12B may be a locking frequency necessary for sampling the video signal, and may be such that it does not exceed the operating limits of each CCD.

In other words, for example, 680-stage CCDs are used as the CCDs 12A and 12B, and the CCDs 12A and 12B are
12 The maximum delay time DLmax of the delay time of the delay circuit configured by B is 85 μsec, and the minimum delay time DL is 85 μsec.
If min is set to 55 μsec and a TBC circuit capable of compensating for jitter components of up to 30 μsec is configured, C
CD12A.

The delay circuit composed of 12B is a 680x2 stage CC.
Since it is equivalent to D, the sampling frequency fs of the output video signal is 16■7~25M from the above formula 0.
Hz. Since this sampling frequency is three times or more higher than the highest frequency of the video signal, aliasing distortion does not occur.

Furthermore, since the clocks supplied to each of the CCDs 12A and 12B at this time are clocks having a frequency equal to the sampling frequency fs of the video signal to be output,
It is a clock of MHz to 12.5 MHz. Since this frequency does not exceed the CCD operating limit of 15 MHz, the CCD can operate satisfactorily.

A switch circuit 19 according to an embodiment of the present invention is configured as shown in FIG. 30.31 and 3 in Figure 5
2.33 indicates an NPN type transistor, the emitters of transistors 30 and 31 are commonly connected to form a first differential amplifier, and the emitters of transistors 32 and 33 are commonly connected to form a second differential amplifier. Ru.

The base of the transistor 30 and the base of the transistor 33 are commonly connected, and the clock input terminal 3 is connected to this common connection point.
4 is connected. The base of transistor 31 and the base of transistor 32 are commonly connected, and a clock input terminal 35 is connected to this common connection point.

The collectors of the transistors 30 and 32 are commonly connected, and this common connection point is connected to the power supply terminal 31 via a resistor 36 and grounded via a capacitor 38. The collector of the transistor 31 and the collector of the transistor 33 are commonly connected, and this common connection point is connected to the power supply terminal 37 via a resistor 39 and is led out as an output terminal 40 .

A common connection point between the emitter of transistor 30 and the emitter of transistor 31 is connected to the collector of transistor 41. The base of the transistor 41 is connected to the input terminal 42, and the emitter of the transistor 41 is connected to the constant current source 43.
grounded via. A collector of a transistor 44 is connected to a common connection point between the emitter of the transistor 32 and the emitter of the transistor 33. The base of transistor 44 is connected to input terminal 45, and the emitter of transistor 44 is grounded via constant current source 46.

The clock input terminal 34 is supplied with a clock CK shown in FIG. 4E from the clock generation circuit 17, and the clock input terminal 35 is supplied with a clock CK having an opposite phase to the clock CK shown in FIG. 4F from the clock generation circuit IT. be done.

The input terminal 42 is supplied with the output of the CCD 12A, and the input terminal 45 is supplied with the output of the CCD 12B.

During a period when the clock CK is at a high level and the clock is at a low level, the transistors 30.33 are on and the transistors 31.32 are off. Therefore, a current flows from the power supply terminal 37 through the resistor 36 and the transistor 30, and this current flows through the transistor 41 and the constant current source 4.
At the same time, a current flows from the power supply terminal 3T through the resistor 39 and the transistor 33, and this current flows through the transistor 44 and the constant current source 46 to the ground. One end of the resistor 39 is connected to the output terminal 40,
The base of the transistor 44 is connected from the input terminal 45 to the CC
Since the output of CCD 12 B is being supplied, at this time, the output of CCD 12 B is taken out from the collector of the transistor 44 and guided to the output terminal 40.

During the period when the ACK CK is at a low level and the ACK is at a high level, the transistors 31.32 are on and the transistors 30.33 are off. Therefore,
A current flows from the power supply terminal 37 through the resistor 36 and the transistor 32, and this current flows to the ground through the transistor 44 and the constant current source 46. At the same time, a current flows from the power supply terminal 37 through the resistor 39 and the transistor 31. ,
This current flows to ground via the transistor 41 and constant current source 43. One end of the resistor 39 is connected to the output terminal 40, and the transistor 410 base is connected from the input terminal 42 to the C
Since the output of the CD 12 A is being supplied, the output of the CCD 12 A is taken out from the collector of the transistor 41 at this time and guided to the output terminal 40 .

Note that although the collector outputs of the transistors 30 and 32 are grounded in an alternating current manner by the capacitor 38, the outputs of each CCD may be taken out as balanced outputs.

[Effects of the Invention] According to the present invention, since a switch circuit having an ECL configuration is used as the switch circuit 19, high-speed switching operation is possible, and analog waveform distortion does not occur. Therefore, according to the present invention, CCD as a variable delay element.
A 780 color video signal circuit can be constructed in which the CCDs are connected in parallel and the outputs of the CCDs connected in parallel are alternately taken out by a switch circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a 780 circuit using a conventional CCD delay circuit, Fig. 2 is a route diagram used to explain the conventional CCD delay circuit, and Fig. 3 is an embodiment in which the present invention is applied to a 780 circuit. FIG. 4 is a waveform diagram used to explain the operation of an embodiment of the invention, and FIG. 5 is a connection diagram of an embodiment of the invention. 2.12A, 12B・・・・・・・・・CCD, 1
0,17°゛・・・・・・・・・Clock generation circuit,
19・・・・・・・・・Switch circuit, 30.3
1, 32, 33, 41, 44 ・・・・・・・・・・・・
transistor. Agent Tadashi Sugiura Figure 1 and Figure 2 1--30. usecJ Figure 3

Claims (1)

[Claims] First and second CCDs having a common input signal are controlled by clocks having the same frequency and opposite phases to each other, and In a CCD delay circuit in which the output of each of the second CCDs is selected and taken out by a switch circuit controlled by the above clock, the collectors of each are cross-connected, and a signal current is applied to each emitter connection point. the signal current sources are controlled by the first and second CCDs, and the clock is connected to the first and second differential circuits; a CCD delay circuit, which supplies the first and second differential circuits with a switching operation to obtain a selected output from at least one collector connection point.