JPS60204191A - Digital signal processor for color television cameracircuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplexed signal component that generates a plurality of signal components that are multiplexed and supplied to one analog-to-digital converter common to each signal component. This invention relates to a television camera having an imager.

[Background of the invention]

Portable color television cameras are commonly used for electronic newsgathering (IIJG) and are becoming popular for home use. The camera currently uses analog video signal processing methods. The synchronous circuit currently has signal levels representing 1 and O (i.e.
Most of them consist of binary circuits (these are sometimes called digital circuits) that use on and off circuits. It is well known that digital circuits can be used to process television video signals such that they represent a larger number of possible amplitude combinations than just two in one circuit. ing. The analogy is eight on-o
Different combinations of ff digital signals can represent the 28 possible amplitudes between types, thereby allowing stable digital circuits to be used to represent the video signal. In addition to being stable, digital formats also allow for forms of signal processing that are difficult or impossible to create in analog formats, such as circuits that exhibit long signal delays without changing the signal amplitude. This can be easily achieved.

The first step in generating a video signal with a camera is to use an imager that converts light from the scene into a signal. A modern television camera uses a color prism and multiple solid-state imagers to produce a temporally quantized image representing the red, green, and blue components of the scene to be transmitted on television. Generating an analog video signal. U.S. Pat. No. 4,167,755
The issue discloses a camera that uses C0D (charge-coupled device) solid-state image detectors to generate red, blue, and green signals under the control of a clock or generator.
It's true. The video signals produced by these imagers (image detectors) are processed in low noise amplifier circuits or double correlated sample and hold circuits under the control of a clock generator, as is well known.

When processing digital signals, analog-to-digital conversion is performed at a single point in the circuit, such as amplifying the analog signal to an appropriate level. Analog-to-digital converters (ADCs) generally suffer from problems such as linearity, range, and offset.

The amount of time involved in analog-to-digital conversion operations, or sampling, is
(4) Must be performed at a frequency at least twice the highest frequency of the input signal to be generated. Considering that the cut-off frequency of the filter is a finite value, in reality,
It is desirable that this ADC be operated at a frequency three times, four times or more higher than the highest frequency of input signal 5.

The input signal is a composite color television signal with a high frequency (3.5 slJ (in the NTSC system) added to the luminance signal).
The ACD operates at a frequency of, for example, 14.3 MHz (2). At such a frequency, the ADC
This poses a problem of high power consumption during operation and associated heat generation.

US! Bi permit No. 4150397, same No. 4163248
No. 71240103 and No. 436408Q
It is well known to use a single analog-to-digital converter for analog-to-digital conversion processing for multiple channels handling the components of a color television system, as disclosed in No. 1, et al. The above US Patent No. 415039
No. 7 and No. 4,163,248 decode the composite color TV signal into each component (in No. 4,240,103, the camera image signal is generated as a component), and each component is then time-division multiplexed to the ADC. sent to for further processing. U.S. Pat. No. 4,364,080 discloses a method of accepting a video signal from an external signal source, processing it into individual video components, and time-division multiplexing each video component and sending it to an ADC for further processing. A digital video analyzer is disclosed. U.S. Patent No. 41632, cited above.
As the inventor of No. 48 points out, time division multiplexing results in a loss of information. This loss is due to the fact that while the multiplexer is supplying a particular signal component to the ADC, signal components that arrive at the same time as the component undergoing processing are lost. It is based on This information loss inevitably manifests itself in low resolution.

To eliminate this resolution loss due to the nature of multiplexed ADCs, in which the ADCs cannot convert the signals of channels to which they are not connected, the scene One ADC can be coupled to receive one signal that collectively represents the luminance and chrominance information of the two. This is done using a camera-based approach, for example, where a single imager is used in conjunction with a well-known color stripe filter or checkerboard filter to generate a signal that changes the display color for each pixel. be able to. However, such single-imager cameras suffer from drawbacks of colorimetry and the low resolution of images obtained due to the large distance between pixels representing a particular color. However, it was not sufficient for high-quality applications. For example, considering the horizontal color pattern RG 13 RG 13, each pixel representing the color green (which is the main component of the luminance signal) is separated by two intermediate pixels.

In order to prevent resolution degradation, for example, U.S. Pat.
Another idea, as shown in US Pat. No. 17,626, is to use three imagers and provide an ADO for each color signal channel.

If one ADC is used for each channel, the required operating frequency of each ADC will be lower than when one ADC is used for the entire composite signal, and the power consumption of each will also be reduced. It may be thought that it will decrease. but,
Each imager of a color camera typically generates signals representing R, G, and B, and these signals are ■ (in-phase) and Q.
, (90 degree phase) signal is a broadband signal (because all three signals are required to form a broadband luminance signal). Therefore, using three imagers, one for each channel, does not significantly affect the required operating frequency. Additionally, the non-linearities and offsets of AI) using a separate ADC for each channel of the camera can cause colorimetric problems.

For example, even if three ADOs (one for each processing channel) were provided with equivalent analog input signals representing RlG and B, the resulting digital signals representing R, G, and B would be nonlinear. Therefore, they may be unequal. These unequal digital signals cause colorimetric problems.

The present invention utilizes digital signal processing methods for portable television cameras because digital signal processing is relatively stable under the environmental conditions such as cold, heat, and shock that the portable television camera encounters. It is based on the recognition that it is particularly advantageous to Furthermore, since the portable camera is battery powered and has low power consumption, it is desirable to have one ADC even if there is one or more signal converters. Even with fixed studio cameras, digital HOT signal processing reduces the need for alignment and
It is preferable to use an ADC because it reduces the number of parts and is advantageous in terms of reliability and cost. 1
The resolution loss encountered with the previously described conventional techniques using multiple ADOs is unsuitable for high definition television applications.

Additionally, the inventor recognized that while analog-to-digital converters are limited in speed, solid-state imagers, such as charge transfer imagers, are even more limited in speed and also limited in resolution. are doing. Thus, cameras with multiple imagers each driving a separate analog-to-digital converter do not take advantage of the speed potential of each analog-to-digital converter, and also The resolution is limited because the number is finite. The inventor also discovered that solid-state charge transfer type imagers such as CCD imagers inherently have an accumulation function that can be controlled by a clock.
They also realized that this could be used to simplify time division multiplexing by providing time delays through simple timing control.

[Summary of the invention]

Within a color television camera, a plurality of imagers generate separate signals representing five images under the control of control signals. These signals from the imager are coupled to the ADO by a time division multiplexer.

To prevent resolution degradation, the clock or imager is controlled so that signals are read from the imager only when the ADC is available.

[Detailed description and examples]

Example 1 In the camera shown in FIG. 1, the lens 10 has color separation'! I
The images formed by the ff prism 18 (■
1) is imaged. A clock and synchronization signal generator 20 clocks the imagers 12, 14 and 16.
11. These imagers are, for example, optical integration register Δ, optical field accumulation register B, and I
It is a field transfer type having storage A + 44 registers C, and each register is controlled by a multiphase clock signal. In the illustrated embodiment, each of the A, B, and C registers (controlled by a 13-phase clock signal) has a total of nine control lines for each imager.

Each solid-state imager is, for example, of the 'heavy transfer COD type' as illustrated in a simplified example in FIG. There is. The photoelectrons are restricted from moving in the lateral direction by a channel stop 94 (movement is restricted to the middle of the longitudinal channel). Therefore, the number of pixels in the horizontal direction is determined by the number of channel stops. Channel stops are made small to accommodate as many pixels as possible horizontally, with current commercial techniques making fewer than 500 pixels per horizontal line. In the imager of FIG. 1a,
The longitudinal motion of the charge is represented by the sign 96, which represents the integrated image.
control type (in return, 11 by the multiphase clock voltage)
11. After the integration period, a clock signal is sent to move the integrated electrons to a corresponding portion of the B register or storage register 98 where they are not affected by the light vj. The electrons in each packet of each horizontal line are clocked in parallel from B register 98 to C register 09 and from there serially by a charge packet representing a pixel or a clock signal applied to clock electrode 97.

With or without a clock signal, the signals in these B and C registers are stored as is.

The operating speed of charge transfer imagers is limited in the vertical direction. Is it normal operation to move charge packets from one potential well or capacitor to the next by a resistive path?This structure discharges one capacitor and then charges the next. This is because it is equivalent to a resistance-capacitance delay line that takes a finite time.

The speed of movement in the water direction 51C is limited by the minimum gate size obtained by photoprinting (IJ printing). As this gate becomes larger (longer in the direction of transfer of voltage 6:i), the outer edge electric field in the region between the gates becomes smaller, so that the electrons present between the potential wells can be directed to the desired well under the control of a clock signal. The force accelerating towards becomes smaller.

Horizontal velocity is also affected by the RC time constant mentioned above.

The outputs of each of the imagers 12, 14 and 16 are fed to well-known double correlated sampling circuits 22-26. This circuit is controlled by a clock frequency comprised by a clock signal generator 20 to accept packets of charge from the imager and generate a low noise video signal therefrom. The clock frequency of the double correlation sampling circuits 22 to 26 is the same as that of the imager 1.
2 to 16 correspond to the frequencies at which the signal samples are clocked. The signals taken out from the sampling circuits 22-26 are passed through amplifiers 28-. . . for amplifying the signals as necessary. The signal representing this amplified image is then applied to a time division multiplexing circuit 34.3 whose switching frequency is controlled by the clock signal generator 20.
6 and 38. The signals selected by the time division multiplexing circuit 40 are transferred to an analog-to-digital converter (AD).
C) applied to 42 and converted to digital form.

This digital image display signal is supplied from the ADC 42 to digital circuitry indicated by blocks (rectangular frames) labeled "Individual correction for one channel" 44 and "Correction common to all channels" 46. Correction circuit 44
The signals processed by and 46 are provided to a digital-to-analog converter (DAC) 48. The sequential color output signal from the digital-to-analog converter is applied to a demultiplexer, shown as switch 50, similar to that operating synchronously with multiplexer 40, which demultiplexes the components from the signal processor. Each is sequentially applied to a sample and hold circuit, which is a time delay or storage circuit exemplified by capacitors 52-56. As shown in the figure, these color components are ](, Y,
Alternatively, analog matrix processing is required following filters 52 to 56, but R, G, and 13. Y, I
, the Q signal is an ordinary N T S signal shown in block 58
C decoder, where the ■ and Q signals individually modulate subcarriers that are in quadrature with each other, and the resulting chrominance signal is summed with the luminance signal to form the ordinary N T SC ( Alternatively, it becomes a PA[,,) signal and is supplied to the output terminal.

As mentioned above, analog 1d generated simultaneously from the imager
The signals are time-multiplexed in a sequential format, converted to digital format, and digitally processed in a time-sequential manner. The processed time-sequential digital signals are applied in serial form to a digital-to-analog converter to be converted into time-sequential analog signals. A time delay after the demultiplexer returns this signal to simultaneous form for subsequent processing. The time order of the color signal can be frame-to-frame, field-to-field, line-to-line, or pixel-to-pixel. Operation at pixel frequency should provide the best combination of properties.

The clocks controlling the processing frequency and switching speed should be kept locked to the color subcarrier signal SC to reduce the possibility of unwanted beats occurring between the sample frequency and the subcarrier of the various circuits. . For example, digital signal processing is performed at approximately 14.3KHz, 4×SC (
This is generally performed at a frequency (4 times the color subcarrier frequency). For this reason, the clock signal generator 20
provides the Δ4XCS clock signal to ADC 42 and other circuitry such as modification circuits 44 and 46 and similar circuits.

Multiplexing switches 40 and 50 are used to apply signals to the digital signal processing portion of the camera during each clock pulse.
must be switched at the same frequency, ie four times the frequency of the subcarrier. Therefore, the switch 40 is set to NTSC (
7) In the case of one cycle of switching (terminal 39, terminals 34, 36 and 38
(connect to each other in sequence).

Similarly, the imagers 12.14 and 16 and their associated double correlated sampling circuits 22.24 and 26 are operated (ie read out pixel samples) at a frequency of four-thirds of the subcarrier. However, in accordance with one feature of the present invention, the imagers are clocked simultaneously, thereby avoiding the loss of resolution due to the loss of two-thirds of the pixels from each imager on each clock. A clock signal generator 20 clocks each imaging
Clock control is performed with a phase difference of 0 degrees. This clock control ensures that readings from the imager occur during times that allow the multiplexer or ADC to process the signal.

The clock frequency is 4/3 x SC and the effective line period is 53 +
55 II l), each imager has 25 per line.
Six pixels can be generated. This number of pixels is commensurate with the number of pixels that can be produced by a conventional solid state imager. In other words, multiplexing the signals from three currently produced solid-state imagers can roughly match the operating characteristics of readily available ADCs.

A comparatively low 4.77 MI from each of the three imagers
- Reading out the pixel signal at the frequency of IZ is balanced with the speed characteristics of each imager, and the phase shift (
readout delay) takes advantage of the storage capabilities of the solid-state imager to create three sequential signals that are time-division multiplexed to produce a signal with a frequency of approximately 14.3 MHz that is commensurate with the speed capabilities of the video ADC. are doing.

Utilizing the storage capabilities of the imager in this manner eliminates the need for auxiliary sample-and-hold circuitry as described in the aforementioned US Pat. No. 4.15039'7. The horizontal resolution of each imager, or number of pixels per horizontal line, is limited to 256 by the sampling frequency of 4.771 VIHz, but this number is determined by the number of channel stops in each imager. is equal to the effective number of photodetectors. Thus, the above-mentioned device 1t is an ADC.
By taking advantage of the limited speed and resolution of solid-state imagers, the linearity, power, and cost advantages of a single ADO can be achieved without the degradation of performance exhibited by multiple image detectors. It is something that can be used to configure a camera.

FIG. 2 shows an example of the control timing between the imager and the double correlation sampling circuit. Figure 2) is the 4xs applied to the entire system in the form of the four bodies f in Figure 1.
FIG. 2(1)) shows the sampling clock waveform 21 applied to the sampling circuit 22.
0, which represents the timing of the clock signal applied to the imager J2 to clock the reading of the signal from the C register of the imager 12. Figure 2 (b
), (Note that (3) and (d) are not actual clock signals, but merely represent timing, since they are applied to the C-Register imagers 14 and 16, respectively, and each sampling circuit It represents the timing of the corresponding clock signal that operates each sampling circuit at the time when it becomes possible to accept the signal from the corresponding imager.

FIG. 3 is a block diagram partially showing the configuration of an embodiment of the clock signal generator 20 shown in FIG. 1 in the form of a specific circuit diagram. In Figure 3, the frequency 'Ill' is four times the subcarrier.
(4X S C) oscillator 3]-0, or repeatedly as the count progresses, takes the form fi O1;
It is connected to 12. The above states are used for clock selection, imager selection, control of the multiplexing switch states and separate digital signal processing states for each channel. The output of oscillator 310 also provides a subcarrier signal SC to encoder 58 and to conductor f for clocking various desotal circuits.
is also applied to a divide-by-4 counter 318 to generate . 4XSC clock signal is A N D gate 320~
324, each one powered by terminal 314.31
6 gates the clock signal on conductors b-d. A N D gate 320 is enabled when its input terminal 326 is high;
This occurs when the gate, 328, is in the active state μs, ie, when the output terminal, 3j6, is high and the output terminal 314 is low. If end r-correction 4 and 316 are high at the same time, A
ND gate 330 is activated and produces a high output, which is applied to the inverting input of AND gate 328 to make it a non-active T step. In all other conditions at terminals 314 and 316, A N D 330 is
If D328 is in the movable state and 316 is high and 314 is low, the AND gate 320 or the pulse 210 ((b) in FIG. 2)
so that it passes through the conductor. Similarly, overall 3
Logic circuits referenced 35 and 340 are Al'
JD 322 is enabled to gate clock pulse 212, and A N 1) 1524 is enabled to gate clock pulse 214. Since the states of both terminals of the counter 312 distinguish between address or clock-controlled imagers, their logic states output the output terminal d.
is coupled through the camera to a circuit that must be synchronized on an imager-to-imager basis to differentiate the signals being processed at that time. Appropriate delay means must be used to match the tallock signal to the signal currently being processed to compensate for delays in the preceding circuits.

FIG. 4 shows details of the multiplexing switch 40, which includes first, second and third transmission gates 410.coupled between input terminals 34.36 and 38 and three output terminals, respectively. 412 and 414. Each transmission gate is enabled by a logic signal applied to its control input. A logic circuit having four AND gates and designated as a whole by reference numeral 420 turns on the transmission gate 410 when 01 or 02 or low in one group and e
When 2 is high and el is low, the transmission gate 412 is turned on, and when both el and 02 are good, the transmission gate 414 is turned on.
Make it n. By reversing the connections to the transmission gates, this circuit of FIG.
Can be used as 0.

FIG. 5a is a block diagram of an arrangement for use in processing signals requiring individual modification for each channel, corresponding to the "individual modification for each channel" block 44 of FIG. This individual modification is termed shading, but includes other types of modification, including defect modification. In the figure l', 5a, the pixels sequentially R, 13, G from the ADC 42
Digital signal is additive black level type control (shading)
is applied to an adder 501 in a well-known manner, and the output signal of this adder 501 is applied to a high-speed digital ROI φ processor 5.
02.

This ROM processor 502 is used to perform gain control type processing for white level control. Processor 50
2 is a taste chart (Robert AclamsD
't; cber t) and Walter (J, M,
The multiplication or high speed multiplication of two video signals in a relatively small memory, as described in U.S. Pat. An example of a processor (multiplier) 502 based on R01φ that performs processing can be configured as shown in a block diagram in FIG. 5b.

The arrangement 502 of FIG. 5b provides pixel-by-pixel control at video rates, which is a channel-dependent correction for multi-channel cameras! The hill is suitable for performing corrections such as shading corrections. To control shading when the video order changes from pixel to pixel in a pattern such as RG, BRGB, etc., the control terminal 51 of the multiplier 502 in FIG.
It is necessary to provide a control signal representing the appropriate shading signal for each pixel.

FIG. 5C is a simplified block diagram showing details of the control signal generator 50.3 of FIG. 5a suitable for generating high speed control signals for the processor 501. Since control signal generators 503 and 504 have similar configurations, only generator 503 will be described. In FIG. 5C, several random access memories (11A1φS) 532.54
2.552 stores information regarding horizontal shading. Although this information is 8-hit information, other number of hits may be used as required.

This horizontal information RAM 5532.542.552 is addressed by horizontal address generator 576. Generator 5
76 receives the clock signal via the conductor a to sequentially address the memory locations of the horizontal information RA IφS, and
The output of the AIVIS is provided with various horizontal positions for each of the red, blue and green imagers (horizontal address generator 576, Meisui 31x A3J). RAM5532.5
Wed) 1 to start addresses 42 and 552
1 reset by a horizontal sync pulse such as a blanking pulse. Horizontal information RAMS 532.542
and 552 need only store a maximum number of words equal to the number of pixels in the horizontal line. In order to reduce the size of this memory, and since the IW image resolution of the eye is not large enough to detect small differences in shade for small horizontal increments, the horizontal address RAM 5532.
Horizontal atlas generator 576 can be configured to change the addresses in 542 and 552 every four pictorials, greatly reducing the required memory storage li. Thus, shading correction is performed in a position IA child form through a predetermined number of pixels. Horizontal address generator 576 also connects horizontal column signal generator 504 (5th C
It is also used to address the horizontal information RAM 5 (not shown).

The control signal generator 503 has a vertical information RAM 5534.544 that stores red, i'f and green shading information.
I also have 554. Vertical information RAM S534
．． 544 and 554 are addressed by vertical address generator 578. This generator 578 counts horizontal synchronization signals, such as horizontal blanking signals, to identify each pixel in the vertical direction, and is reset by a vertical blanking pulse applied to a reset input terminal. Vertical information E? The output of the AMS is information regarding the vertical shading for each of the three primary colors. The vertical and horizontal information for each of the red, H, and green channels are provided to adders 536, 546, and 556, respectively, where they are added together before being sent to multiplexing circuit 56.
0 (indicated by a dashed frame). This circuit 560 is
It is shown in the form of a multi-bit, single-pole, three-throw switch that applies a common output to the control input terminal of processor 501. The multiplexing circuit 5 (io is connected to the terminals as already explained in connection with FIG.
2 given by the clock generator via re1 and 02
Controlled by a human input signal. Since there is a delay in the signal processing path, phase adjustment is required and is performed by phase adjustment block 561.

Vertical and horizontal information RAIφS 532 554 includes:
The information is entered during the setup process prior to the actual operation of the camera for scene imaging. This information is determined in large part by the characteristics of the imager, or these imagers are relatively reliable and change little over time. Accordingly, the information stored in the RAMS 532-554, once stored, is readily available for very long periods of time. Therefore, a keep-alive circuit indicated at 580 is provided, which includes a battery 581 to keep the J,'(A Yes.RAM55
The information required by 32-554 is provided by a keyboard 572 operated by a camera alignment technician and a color microprocessor 570.
The technician uses the keyboard 5']2 to specify various addresses and the amount of shading to be used at each address.

For some purposes, it may be useful to use an analog-to-digital converter in the form of an axis converter, such as shown at 574, to indicate the degree of shading correction to be used at a specified location. It may happen.

Details of digital apparatus for controlling gain, pedestal, gamma and other parameters are shown in U.S. Pat. No. 4,396,938 to Teischert. As described in the above-mentioned U.S. patent, the digital signal
fvl S is given as an address alternately,
The output is represented by the peaks and valleys of its address RAM.

While one FIAM is being addressed and read by the input video signal, the other RAM is receiving new program values representing pedestal, gain, gamma, etc. Such a device can be used for modifications common to all channels, ie as block 46.

Embodiment 2 Another embodiment of the invention is shown in FIG. 6, using two imagers. In FIG. 6, lens 6
10 directs light from an image (not shown) to prism 6
18, the green component of the light enters the imager 614, and the remainder enters the checkerboard or striped color filter 6.
12 to form an image on a second image pickup device 616 in a human-like manner.

The output signal from the imager 614 is provided to a dual correlation sampler circuit jll,'i 624 and the output signal from the imager 616 is provided to a similar circuit 626. As in FIG. 1, these signals are amplified by amplifiers 630 and 632.

If imagers 614 and 616 are clocked simultaneously, imager 614 will generate samples representing the green component of the light from the image each clock cycle, while imager 616 will simultaneously generate samples representing the red, blue, and blue components of the light from the image. Vixels representing red, blue, etc. are generated alternately. clock generator 620
is a temporally continuous GR using clock control of both imagers.
GBGRGB... is generated, but in order to do so, both imagers must be read alternately (i.e., with a phase difference of 180 degrees instead of a phase difference of 120 degrees as in the example in Figure 1). It is necessary for the multiplexing circuit 634 to alternate at the same frequency to select the appropriate signal. Such alternating operation will be obvious to those skilled in the art upon reference to the description of the clock signal generator in FIG. 1, and will therefore not be described in detail.

The green signal from amplifier 630 and the alternating red and blue signals from amplifier 632 are arranged in a time-sequential serial format by a multiplexing circuit 634 and are converted into time-sequential RGB signals by an ADC 642.
GRGBG...processed to form a signal,
The signals are processed by digital signal processors 644 and 646. Minor modifications to the address logic required for a slightly different order will be obvious to those skilled in the art. This time-sequential digital information is 1] applied to an AC and sample-and-hold circuit 648 to form an analog signal and to an encoder 658 to form a composite signal that is provided to the utilization means. The subcarrier modulated by the encoder (), ") F (or color signal) is divided by a frequency divider 67 which divides the frequency of the 4xSc clock signal.
Supplied from 0. 7(''C642 or 4 XSC(]
, 44.3M1-IZ), and each imager is clocked at 2XSC (7,161M1-IZ). During the valid period 53.567zS, the imager outputs '
Approximately 358 pixels can be read out at a frequency of 161Vil-IZ.

6, the configuration of FIG. 6 alternates between green (mostly the signal 74" representing luminance) and red or blue (on a different alternating basis) from the imager's storage lens at low speed. The multiplexing circuit doubles the frequency of the signal applied to one ADC to better utilize the speed capabilities of the ADC. It also allows a single ADC to process multiple signals, reducing cost, power consumption, and errors.

As discussed with respect to the figures, single channel digital signal processing schemes are particularly advantageous when used with a single ADC. Is it necessary to use a decomposer that distributes the output of the ADO to multiple digital signal processing channels?11
1 (and because the component count is very low, resulting in reliability l'i':I). Such a single-channel digital processing scheme is also very advantageous. [11]] This is because there is no color error due to differences between A and C. For example, five equal digital signals representing RSG and B may not result in equal analog outputs, but Since a single multiplexed DAC always produces equal output signals from equal input signals, color errors do not occur.

Embodiments of the invention other than double inversion will be obvious to those skilled in the art. For example, while the video words in the embodiments described were represented by 8-bit signals, it is also possible to increase or decrease the number of hits, or each channel could have a different number of hits (i.e., green...・8 bits, blue...4 bits, red...6 bits, etc.) can also be used. The clock frequency of A is a matter of design choices and the speeds achievable with current technology.

The video switch, illustrated for convenience as a mechanical switch, can be constructed from solid state components appropriate to the actual operating speed. Some delay circuits include multivibrators, glass or CCD slow wires, transmission lines, and other forms.

Although the illustrated embodiment uses doubly correlated sampling to extract low noise signals from the imager, other suitable methods may be used.

It is also possible to multiplex signals such as audio signals with video signals. Among such other signals are signals representing monitor signals (power supply voltage, temperature, etc.) that are generated at the location of the pickup device and that may be necessary to monitor at other locations.

4., Brief Description of the Drawings FIG. 1 is a simplified block diagram of an example of a three-imager type camera according to the present invention, and FIG.
Figure 2 is an amplitude versus time diagram showing clock signals at various parts during operation of the camera with the configuration shown in Figure 1, and Figure 3 is a diagram showing the lock signal generated as illustrated in Figure 2. 4 is a simplified block diagram showing an example of a multiplexing circuit used in the camera of FIG. 1, and FIGS. 5a to 5C are FIG. 6 is a block diagram showing the structure of an example 2 imager type camera according to the present invention.

10... Lens, 12.14.16... Imager (image detection means), 18... Color separation prism, 20... Clock signal generator (control signal means), 40... Multiplexing Circuit, 42... Analog-to-digital converter (analog-to-digital signal conversion means), 44... Individual corrector for channels (signal processing means), 46... Corrector common to all channels, 48... Digital-to-analog converter, 50... Demultiplexer (demultiplexer), 58...
・Encoder.

Patent Applicant: RCSNY Corporation Representative: Satoshi Shimizu Haka2 d) 214 years old 2 Figure L

Claims (1)

[Claims] (1) a plurality of N flaw detection means each comprising an array of pixels from which an image signal can be retrieved by application of a clock signal; an analog-to-digital signal converting means for generating a signal, the multiplexing means being coupled to the input of said analog-to-digital signal converting means and said plurality of flaw detection means; said a several flaw detection means and said plurality of flaw detection means; coupled to analog-to-digital signal converting means and said time multiplexing means, said means for operatively operating said flaw detection means at a first speed; operating at a second speed equal to N times the speed of said analog -
The time multiplexing means is operable to produce a series of N interpolated samples occurring at the second rate for application to the digital signal processing means and the analog-to-digital signal converting means control signal means for enabling said second speed to operate;
A digital signal processing device for a color television camera, comprising: signal processing means coupled to an output terminal of the analog-to-digital signal conversion means for processing the digital signal obtained therefrom.