JPS60206067A - electrode wiring - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an electrode wiring for a semiconductor, and particularly to an electrode wiring suitable for improving resistance to heat treatment in a manufacturing process and improving reliability of a semiconductor element.

[Background of the invention]

In recent years, as the miniaturization of semiconductor devices has progressed, the width of wiring in semiconductor devices has become significantly smaller, and as a result, many problems such as electromigration have started to occur.

In order to solve such problems, for example,
Many methods have been proposed, such as No. 31619.

However, these conventional methods J1! ! However, it has been difficult to effectively prevent the occurrence of disconnections and short circuits.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and provide a fine electrode wiring for a semiconductor device that is free from the risk of disconnection or short circuit and has high reliability.

[Summary of the invention]

In order to achieve the above object, the present invention adds a metal capable of forming silicide to Ω to prevent electromigration, and also provides a layer between the AQ layer and the Si layer to prevent an increase in Si. This is to prevent the reaction between St and the wiring, and to prevent problems that may occur due to the addition of the above-mentioned metals.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using Examples.

Example Ten types of samples shown in Table 1 were prepared and their heat resistance was examined.

The sample preparation method will be explained using drawings for a typical #3°5.8 sample. #1, 2, and 3 are electrode wirings having a known structure, and basically have the structure shown in FIG. Openings 17.18 are provided in the insulating films 13.14 formed on the substrate 5i15 and the polycrystalline St 14, and the three-layer wiring films 10 to 12 are deposited by sputtering, followed by normal fusing. The wiring pattern was created using an etching process. The sample $2.3.4 has a three-layer structure, and the middle Ta or W layer 12 is the upper and lower AQ or AQ.
It was formed continuously in the same chamber as the -8i layer 10.11.

Samples #5 and 6.9 basically have the structure shown in Figure 2. Openings 27 and 28 are formed in the insulating films 13' and 14' formed on the St substrate 15' and the polycrystalline 5t14'.
In No. 9, MoSi 2 was deposited to a predetermined thickness by sputtering. In sample #9, compound crystallization of MoSi 2 was promoted by H 2 annealing at 550°C. after that,#
For Nos. 5, 6, and 9, a wiring film was formed in the same process as #3°, and the wiring was patterned. When etching the wiring, W-10% Ti, Mo, and MoSi2 formed under the wiring are etched at the same time. Therefore, these films remain in all parts under the wiring.

The $7.8.10 sample basically has the structure shown in FIG. The sample of x sail a is on the substrate 16#, polycrystalline 5i
15; Provide openings 36°37 in the upper insulating film and select CV
A W film is formed only on the opening by method D. Sample #8 is subjected to H2 annealing at 700° C. to convert a part of W in contact with basic 16' or polycrystalline 5ii5' into a compound 33.34 with St. Since the sample No. 9 of 31 and 32 degrees, in which the upper layer of W remains as W, is not heat-treated, compound layers 33 and 34 are not formed. For the #lO sample, an opening is provided in the insulating film in the same manner as above, and then Pt is deposited by sputtering.

Compound P of Pt and St was formed by N2 annealing at 400°C.
tSi was formed only at the contact portion with Si. Thereafter, unreacted Pt was removed with aqua regia. Therefore, in this sample, S
Compound layers 33 and 34 of t and pt exist, but unreacted layers 31 and 32 do not exist.

For the #7.8°10 sample in which the electrode portion was formed in this manner, a wiring pattern was formed by the same process as #3.

The sample prepared as described above was subjected to N2 annealing at 450° C., and the disconnection of the wiring electrode and the short circuit failure rate were measured. The defective rate was determined by measuring the resistance of each of 500 wires including the connection portion with a pair of substrates Si and the connection portion with polycrystalline St. Note that the size of the opening in the connecting portion is 1.5 Xl and 5 μm. The results are shown in Figure 4.

As is clear from Fig. 4, #1~ having a well-known structure
In No. 4, most of the wirings became defective after a short heat treatment, but in the wiring No. 5 to No. 10, the failure rate of short circuits and disconnections was much lower, and a remarkable improvement effect was observed. In particular, no defects occurred in wiring #5 to #9. It was found that 90% or more of the failure modes occurring in wiring #1 to #4 were short circuits. When these short-circuited samples were observed by SEM, it was found that St reacted with the wiring. In addition, when we analyzed the intermediate layer that remained after removing AQ by etching for wiring #2 to #4 by electron beam diffraction, it was found that in the film #2.3, TaS
It was confirmed that iz was due to the formation of silicide with Si, Ga, etc. in the #4 film.

On the other hand, in the present invention, as shown in FIG.
Since the metal or silicide layers 31 to 34 are interposed between them, the reaction between Si and the electrode wiring is effectively prevented, and there is no possibility that silicide will be formed due to the reaction.

As a result, in the present invention, as shown in FIG.
The defect rate is much lower than that of conventional interconnect structures, making it extremely effective in improving the reliability of semiconductor devices.

As described above, the present invention adds an element that can form a compound with Si to the AQ wiring to prevent electromigration, etc., and to prevent the disturbances caused by the addition of the above elements from being transferred between St and the wiring. This is prevented by interposing a layer of metal or its silicide.

Therefore, the above element added to the AΩ wiring is S.
Many elements that can react with i to form silicides can be used.

For example, Ti, Znt, Hf, V, Nb, Ta.

Cr, Mo, W, Mn, Tc, Re, Fa, Ru.

Os, Ce, Rh, Ir, Ni, Pd, or pt can be used alone or in combination.

Ti, Zr, Hf, V, Nb, Ta, Cr.

Particularly favorable results are obtained when at least one of Mo or W is used, and it goes without saying that alloys of these elements can also be used.

These elements may be added uniformly into the AQ wiring, or the wiring may be formed by sandwiching the upper and lower layers of these elements formed in the center with Af1 layers.

When uniformly added to the AQ wiring, the range of the amount of the above-mentioned element added is approximately 0.1 to 5 atomic percent.

If the content is less than 0.1%, the effect of suppressing the electromigration will be small, and if it is more than 5%, the increase in electrical resistance will become significant. It is preferably atomic %.

Further, when forming a layer of the above element in a sandwich shape in the center of the wiring, the thickness of the layer of the above element varies somewhat depending on the thickness of the wiring.

However, if the total thickness of the wiring is approximately 1 μm or less,
Favorable results can be obtained if the thickness of the layer of the above elements is approximately 50 to 1,000 layers.

In addition, as the transition metal interposed between the wiring and St or the transition metal in the silicide layer thereof, it is preferable to use the same element as the above element that can be added to the wiring width.
Particularly favorable results are obtained when Zr, Hf+VgNb+Ta, Cr, Mo, W or at least one of these silicides is used. Also Pt or P
Even if a layer of silicide (d) is interposed, very favorable results can be obtained as well.

If the thickness of these layers is too thin, the effect of suppressing the reaction between St and the wiring will be insufficient. Even if the film thickness increases, there is almost no negative effect on the device, so the upper limit of the film thickness is
Depends on the manufacturing process.

For this reason, the film thickness is usually about 500 to 2 μm, but there is no problem even if it is thicker than this.

〔Effect of the invention〕

As described above, according to the present invention, problems such as electromigration caused by miniaturization of wiring can be effectively prevented, and reactions between the wiring and Si can also be prevented, so wiring of semiconductor devices with high integration density can be prevented. It is extremely useful as a

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional view showing a conventional wiring structure, FIGS. 2 and 3 are partial cross-sectional views showing different embodiments of the present invention, and FIG. 4 is a curve diagram showing the effects of the present invention. be. 10.16', 16'...substrate, 13.13'. 13', 14.14', 14'...Insulating film, 10°10', 10', 11.11', 11'...
・AQ distribution 1 8 Figure 2

Claims (1)

[Claims] 1. In an An wiring containing an element that forms a compound with Si as an additive element, a transition metal, or a combination of a transition metal and Si, is used at least between the wiring at the connection part with the substrate Si or polycrystalline St, and the St. An electrode wiring containing in a layered form at least one of the following compounds, wherein the transition metal is an element of groups IVa+ Va+ Via, ■a, and ■ of the periodic table.