JPH04130727A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To eliminate that impurities are piled up when a target is added and to add high-accuracy impurities without affecting an etching operation by a method wherein an Al-Si-based alloy is etched and formed as a wiring layer, a Cu film containing Hf and B is then formed only on the surface of Al wiring part by an electroless plating method and an Al-Si-Cu-Hf-B alloy wiring is formed by a heat treatment. CONSTITUTION:An interlayer insulating film 2 is formed on an IC substrate 1 by a CVD method; a flow heat treatment for flattening is executed; after that, an Al-Si-based alloy film which is to be used as a wiring layer is formed by a sputtering method; and a wiring pattern is formed by a photolithographic technique or an etching technique. After that, this assembly is immersed in a PdCl2 solution. Thereby, Pd 14 is adsorbed only to the Al wiring 3 which contributes to ionization; and the surface of Al is activated. Then, a Cu film 15 which contains Hf and B is formed by an electroless plating method. After that, a passivation film 4 is formed by a CVD method; and it is annealed (heat- treated) in a hydrogen atmosphere. Thereby, a semiconductor element whose wiring layer 3 is formed of an Al-Si-Cu-Hf-B alloy is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to the manufacture of semiconductor devices, particularly to the formation of wiring layers thereof.

(Prior Art) A wiring structure in a semiconductor element is conventionally formed as shown in FIG. First, an insulating film 2 (for example, BPSG) is formed on an IC substrate 1 having a diffusion layer etc. by the C2 method. Thereafter, an Al-5L alloy film 3, which will become wiring, is formed by sputtering, and a wiring pattern is obtained by bottlingography and etching techniques. Thereafter, a coating film 4 (for example, 5iN) is formed by CVD. This completes the semiconductor device.

However, as the degree of integration increases, the interconnect width increases.

As the wiring spacing becomes narrower, various problems are occurring. Some examples include wire breakage and Al loss due to electromigration and stress migration, intralayer shorts due to hillock formation, and shorts between the eyebrows. To solve these problems, by adding impurities into l', Al
Methods of improving film quality are commonly used. The elements are (u, Tj.

Although there are various materials such as Pd, Hf, B, N, O, etc., Cu is particularly representative. In recent years, Cu and other elements (such as Hf) have been introduced.

B) is added to form an A1-61-Cu-, Hf-B film to strengthen the wiring. The formation method is as described above, after forming an insulating film on the IC substrate, Aj-3t-Cu-H
Al-S by sputtering using f-B target
i-Cu-Hf-B film was deposited, bottlingography,
The etching technique is followed by patterning to form a noxification film to complete the process. As a result, a highly reliable A7 wiring in which hillocks are difficult to form can be obtained.

(Problem to be Solved by the Invention) However, in the case of the above method, since the amount of additives in the AI gold alloy is controlled by the composition of the target, the amount of Cu, Hf, and B contained in the sputtered film increases with the amount of target used.
Not only does the amount of added impurities such as the I end up uploading my mother. In this way, the added impurities are not uniformly distributed in AI! RIE or EDR the membrane
When etching is performed using a method such as etching, it is not able to cope with quill-up and not only remains as a residue on the insulating film, but also causes corrosion phenomena. Furthermore, even if a target is created to increase the amount of impurities such as Cu, Hf, B, etc. added in order to further strengthen the l' wiring and an Al film is formed, etching will cause problems such as residue and corrosion as the amount of impurities increases. There is a problem in that the wire becomes even larger, making it difficult to form fine wiring.

(Means for Solving the Problems) This invention solves the problems of pile-up of impurities in the film due to sputtering conditions when using the above-mentioned impurity doping target and difficulty in forming fine wiring due to an increase in the amount of doped impurities. In order to remove the wiring layer, a normal Al-Si alloy film was formed, a wiring pattern was formed using photolithography and etching techniques, and then electroless plating was used to form a layer containing Hf and B. A Cu film is selectively formed only in the wiring layer portion to strengthen the wiring layer.

(Function) Since the present invention uses the method described above to form a wiring layer, there is no pile-up of impurities caused by conventional target addition, and high concentration impurities can be added without affecting etching. . Furthermore, since the Al wiring surface is formed of an alloy layer mainly composed of Cu, it is more resistant to stress than the AIV alloy, and the occurrence of defects, hillocks, etc. can be further suppressed.

(Example) FIG. 1 shows a process sectional view of the main parts of an example of the present invention. First, as shown in Figure 1, an interlayer insulating film 2 (for example, BPSG) is formed on the IC substrate l by CVD method at 6000×.Then, a flow heat treatment is performed to flatten the film. Do minutes.

After the flattening, an Al-Si alloy film 3 that will become a wiring layer is formed at 6000× by sputtering, and wiring/? form a turn.

Thereafter, a Cu film is formed using an electroless plating method.

First, in order to activate the surface of )l, it is immersed in PdC7I2 solution for 1 minute. The composition of the PdC42 solution is PdC/20
．． 05 to 0.2 g/l dissolved in a slightly hydrochloric acidic aqueous solution. As a result, Pd j 4 is adsorbed only to the A/wiring 3 portion that is subject to ionization, and the Al surface is activated.

Next, as shown in the figure (b), a Cu film containing Hf and B is formed by electroless plating. The composition of electroless plating solution is
Cu5O at O-01~0-1 mol/l, Hf0C
J2 at 0.001-0.05 mat/l, DMA
B (trimethylamineporan: (CH3)2NHBH5
) 0.01-0.1 mol/l, EDTA (
ethylenediaminetetraacetic acid) O05~02mo///l
Then, adjust the - to 8-1o with ammonia. The liquid temperature is 60-90°C. By immersing it in this plating solution, the Cu film 15 is formed only on the Pd 14 on the A/wiring 3.
200-500X is formed. That is.

Pd 14 acts as a catalyst. This Cu film 15 has H
F and B are contained, and the concentration thereof can be changed depending on the amount of HfOCl2, etc., and -. Afterwards/I
CVD method 11C terrorism for P Tsujibation film 4 000
By forming the wiring layer 3 to a thickness of
A 4-Si-Cu-Hf-B alloy semiconductor device is completed. In addition, reagents for adding Hf include water-soluble Hf(S04)2 and other reagents other than If OCI2.
A similar effect can be obtained with a reagent containing f.

Further, it goes without saying that the present invention can be applied not only to the first wiring layer but also to two or more wiring layers of multilayer wiring.

(Effects of the Invention) As explained above, according to the present invention, after forming a wiring layer by etching a normal Al-8L alloy, a Cu film containing Hf and B is applied to the AIV wiring layer by electroless plating. Al-8l-Cu-
Since the Hf-B alloy wiring is used, there is no impurity build-up caused by conventional target addition, and high concentration impurities can be added without affecting etching. Furthermore, since the surface of the Al wiring is formed of an alloy layer mainly composed of Cu, the Al-gold alloy also becomes more resistant to stress, and the occurrence of defects, hillocks, etc. is well suppressed. Furthermore, by changing the plating time, the I value, and the amount of HfOCl2 added, it is possible to control the Cu film thickness and the Hf and B concentrations.

[Brief explanation of drawings]

FIG. 1 is a process sectional view of an embodiment of the present invention, and FIG. 2 is a structural diagram of a conventional example. DESCRIPTION OF SYMBOLS 1... IC board, 2... Insulating film, 3... Wiring layer,
14...Pd, 15...Cu0 Fig.

Claims (1)

[Claims] As a method for forming a wiring layer of a semiconductor element, (a) an insulating film is formed on a semiconductor substrate, and an Al wiring layer is formed on the insulating film on the semiconductor substrate.
- a step of forming a Si-based alloy film, (b) a step of forming a Cu film containing Hf and B on the surface of the wiring layer by electroless plating after forming the wiring layer, and (c) a subsequent step of heat treatment. , the wiring layer is made of Al-Si-
A method for manufacturing a semiconductor device, comprising the steps of: forming a Cu-Hf-B alloy.