JPS60206268A - Synchronous clock generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a synchronous clock generation circuit for receiving a serially transmitted data string and thereby generating a clock signal synchronized with the serial data. More specifically, the present invention relates to a synchronous clock generation circuit suitable for receiving teletext signal data, synchronizing with it, and generating a thick signal.

[Background of the invention]

As is clear from the signal format in one horizontal period (IH) shown in FIG. 1, the teletext signal has a pit synchronization signal, a frame synchronization signal, and a data identification signal inserted as a header immediately before the information data. This can be seen, for example, in the Journal of the Television Society (1980), Vol. 34, No. 10, P.
7.

To extract the teletext signal, it is first necessary to generate a clock signal synchronized with this bit synchronization signal.
A common method is to digitally sample and extract the teletext signal (information data) that follows the bit synchronization signal using the static signal.

In the conventional technology, a clock signal of 5,73Mllz, which has a frequency equal to the bit rate of the teletext signal, is first generated, and by passing this through a delay circuit, a clock signal of the same frequency (5,73M)Iz), which differs only in phase, is generated. A large number of sets of signals are generated as multiphase clock signals, and the multiphase clock signal is generated at a timing synchronized with a start pulse signal (hereinafter referred to as an STX signal) generated in synchronization with a bit synchronization signal included in a teletext signal. By latching each logic level of and examining the latched values, only one specific clock signal having a phase relationship closest to the phase of the bit synchronization signal is selected from among the multiphase tally signals. is used as a synchronous clock signal.

FIG. 2 is a circuit diagram showing such a conventional synchronous clock generation circuit. In the same figure, 1 to 7 are buffers (delay elements), 8 to 15 are D-type flip 7p tubes, and 16 is a gate OM ( read-only memory), 17.18
are multiplexers, 19.20 are input terminals, 22 to 29 are multiphase clock signals, and 30 to 37 are 8
is a bit-parallel signal.

FIG. 3 is a waveform diagram showing an example of the waveforms of the multiphase clock signals 22 to 29 in FIG.

The circuit operation will be described with reference to FIGS. 2 and 3. In FIG. 2, buffers 71 to 7 are used as multistage delay elements and constitute a multiphase clock generation section.

Now, input the reference signal OSC of 5.73 Muz to the input terminal 19.
When input from the buffer 1, a clock signal of the same frequency (5,73 Ml1z) whose phase is different by the delay time of one buffer can be obtained from the output of the buffer 1.

This delayed click signal is sent to the subsequent buffer 72~
7, it is possible to generate multiphase click signals 22-29 having different phases from each output side of each buffer 2-7.

Next, in the data extraction phase determination section consisting of latches 8 to 15 and 0M16, polyphase thick signals 22 to 29 outputted from the terminal 19 and the output side of buffers 1 to 7 are sent to latches 8 to 15.
5, while the aforementioned S synchronized with the bit synchronization signal
A TX signal is obtained by some means not shown and is inputted and supplied from the latch pulse input terminal 20.

As can be seen from FIG. 3, when the STX signal is input at a certain timing T, the latches 8 to 15 receive the multiphase clock signal 22.
8 tQ J21 at that timing of ~29! The level is latched and input as 8-bit parallel signals 30 to 37 to the address input terminals AO to A7 of the 0M16. Inside the box 0M16, according to the addresses Ao and A7, the lock signal (i.e., the clock signal 26 that first produces a rising edge to the right of the input timing T of the STX signal in FIG. 3) for data extraction is the next one. Stage click phase selection section (multiplexer 17, 18)
Output 4 bits A of 0M16 to be selected.

B, C, and D are defined.

In other words, in FIG. 3, the input timing T of the STX signal is the timing that is synchronized with the data string to be sampled (more specifically, its bit synchronization signal), as described above, so the input timing T of the STX signal is the closest to this timing phase. The phase-related clock signal 26 is considered suitable as a synchronous signal for sampling the data string.

This will be explained in detail below. As already mentioned, the input timing T of the STX signal and the multiphase clock signals 22 to 290
Assuming that the phase relationship is as shown in FIG. 3, the latched 8-bit parallel signals 30-37 are HHHHLLLL.
It becomes L. This 8-pit latch output HHHHLL L
When the L signal is given to the address input terminal of 0M16, the data output (4 of A, B, C, D) of 0M16 is
The corresponding data output (A , I3.C, D) are determined. Table 1 shows an example of the relationship between the input and output signals of the ROM 16 that satisfies such requirements.

Table 1: The clock phase selection unit consisting of multiplexers 17 and 18 is explained below.Table 2: An example of the input/output signal relationship of the clock phase selection unit.Table 2: 0M16 output signals A, B, C is multiplexer 17
becomes the selection designation input signal, and its data input DO-D7
Select which data input is to be output to the output terminal Dx from among the following. When the data input to be output to the output terminal DX is determined, its inverted output appears at the Dx terminal.

The output signal (bit) D of ROM16 is sent to multiplexer 1.
When the D bit is II, the data input Dx is selected, and when the D bit is L, the data input DX is selected and output from the output terminal 21. The physical meaning of this is that in FIG. 31, when the input timing T of the STX signal is within the period I, the Dx of the multiplexer 17 in FIG.
When the output is output from the output terminal 21 and the input timing T is within the period ■, the D of the multiplexer 17 is
This means that the x output is output from the output terminal 21. It will be seen from FIG. 3 that the sum of periods I and ■ corresponds to exactly one period of the clock signal.

In this way, in the end, a total of 16 sets of clock signals, consisting of 22 to 2908 sets of clock signals shown in FIG. A clock signal is prepared within one cycle of the rip-tock cycle (175nSeC), and one of them is
The set of clock signals is selected as the synchronous clock signal.

Now, in the conventional synchronous clock generation circuit described in detail above, the 08TX code has the following problems related to the generation of STX signals. This is a start pulse signal generated in synchronization with the included bit synchronization signal, and the method for generating this STX signal is to prepare a counter that counts it as a bit synchronization signal rough lock pulse train, and to When a clock pulse (pit synchronization signal pulse) is commanded and counted, the count output is set to change from L to H at the same timing as the edge of the pulse that has finished counting, and such a count output is used as an STX signal. There is.

However, in the case of such a method, in FIG.
Each logic level of the multiphase clock signals 22 to 29 is latched in the latches 8 to 15 at the timing of the signal.
Once per horizontal scanning period (IH), if the bit synchronization signal fluctuates in the time axis direction due to noise or transmission distortion, the timing T of the STX signal will fluctuate in the direction of the arrow in Figure 3, and as a result it will be latched. The data may become erroneous, such as when it is originally supposed to be H, or when it is H, it becomes L.

In this case, the clock phase selection section selects the click phase based on the incorrect data, which may result in selecting a non-optimal phase difference signal.

[Purpose of the invention]

The present invention has been made in order to improve the problems of the prior art as described above, and therefore, an object of the present invention is to prevent bit synchronization signals included in teletext signals from being affected by noise, transmission distortion, etc. on the time axis. To provide a synchronous clock generation circuit which can always select and generate a clock signal with an optimum phase even if there is some variation in the direction.

[Summary of the invention]

The key point of the present invention is that, in the D-type 7 lip-flops 8 to 15 in FIG. By determining the logic level of the polyphase click signal at a timing point multiple times and latching it according to the majority of the determination results, it is possible to detect when the bit synchronization signal temporarily fluctuates in the time axis direction due to noise or transmission distortion. However, the point is that erroneous data is not latched, so that the subsequent selection of the optimal phase clock signal is not adversely affected.

[Embodiments of the invention]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a circuit diagram showing an embodiment of the present invention. In this figure, the same elements as in FIG. 2 are designated by the same reference numerals. In addition, 41 is an inverter, 42 is an exclusive N
OR circuit, 43 is 3-man power AND'/'), 44 is 4
Stage binary counter, 45 to 52 are latch circuits, 53 and 54 are input terminals, 55 is a C edge signal, and 56 to 63 are counter outputs (latch outputs).
, is.

This embodiment differs from the conventional example shown in FIG. 2 in the circuit configuration of latch circuits 45 to 520 and the input circuit of C(+F). Therefore, these differences will be explained below. .

The near 5, C ratio signal is an abbreviation for clock run-in signal, and is generally called a bit synchronization signal, but in the technical field of teletext broadcasting, it is not called a bit synchronization signal. Since it is called the C ratio signal, C
R ratio signal ◎ FIG. 4 is a waveform diagram showing the signal waveform of the main part in FIG. That is, as shown in FIG. 11i4A, it is assumed that the C ratio signal is inputted from the input terminal 53 as consisting of four pulses.

The CR ratio signal is input directly to one input side of the exclusive NO converter circuit 42, and is inverted via the inverter 41.
The R ratio signal is supplied to the other input side of the exclusive NOR circuit 42.

When the delay time due to passing through the inverter 41 is τ, the output signal C of the inverter 41 has a waveform as shown in FIG. 4A. Therefore, the output of the exclusive NOR circuit 42 becomes eight pulses generated in synchronization with the rising edge and falling edge of the CR ratio signal (this is the C edge signal 55) as shown in FIG. 4A. .

Return to Figure 4. The CR edge signal 55 thus generated is applied to one input of the three-man AND gate 43. On the other hand, the four-stage binary counter 44 initially
Since it is cleared by the clear signal CLR input from 4, the fourth stage output 4D is outputting L. Therefore, the inverted output 4D outputs H, which is the result of the three-person AND
The power is applied to one of the two remaining gates 43.

Therefore, if the logic level of the clock signal 22 applied to the remaining one of the three-man power AND gates 43 is H, then 3
Human AND gate 43 produces an output when the logic level of CR edge signal 55, seen in FIG. 4A, is [I. The CB edge signal 55 consists of 8 pulses and therefore becomes H eight times, so if the clock signal 22 was at the I-level at all eight times, the CB edge signal 55 is made up of eight pulses.
The ND gate 43 generates eight outputs, and when the counter 44 counts the eight outputs from the AND gate 43, its fourth stage output 41) changes to Ii, and 4D changes to L. .

That is, if the logic level of the clock signal 22 is H at each timing over eight or more /ζζs generated as the CR edge signal 55, the counter 44
The fourth stage output 4D becomes H, which is the counter output 56.
As ROM160A.

It is input to the terminal.

In addition, in FIG. 4A, 4 CB double signals and 5 C double edge signals
5 shows only 8 pulses, but in reality there are many more, for example, 8 for the C edge signal and 16 for the CR edge signal.0 Since the circuit is configured like this, the clock signal 22 CR 16 as edge signal 55 (
li! Of the pulses, 8 or more pulses, which are half of them, will be successfully detected as H, so if that happens, the fourth stage output 4 of the counter 44 will be Df:H.
Next, the clock is input to the 0M16 with the logic level of No. 22 being H. Thereafter, the 4D output of the counter 44 becomes L, so the three-man power AND gate 43 is closed.

In this way, even if the logic level of the clock signal 22 is originally H but may be temporarily detected as L, it will not be erroneously taken into the 0M16 as L. The same is true when the original value is temporarily detected as H; in this case, the 4D output is L and never becomes 11.

The same holds true for the other latch circuits 46-52.

Table 3 shows the operation results of the circuit in FIG. 4 when the timing T in FIG. 3 includes fluctuations in the time axis direction (that is, when the CR edge signal 55 in FIG. 4A is subject to fluctuations in the time axis direction). Give an example.

(Margins below) Table 3 From the phase of timing T in Figure 3, even if the timing T (the time axis of the CR edge signal 55 in Figure 4A) fluctuates, the signal D□-D2 is almost not detected as I ( , the probability that there is a big change like the 10th time in Table 3 and the overall result is L is very small, and if a majority vote is taken, a big change like the 10th time will be ignored.
Does not affect counter output.

Similarly, the majority decision result for signals D5 to D7 is L. Also, signal D3 has a higher probability of being detected as L due to fluctuations in timing T than Do-D2, but considering that timing T in FIG. more often than not,
The result of majority vote is H. Similarly, the signal D4 becomes L.

Therefore, when considered as a whole, large fluctuations such as the 10th fluctuation in Table 3 are canceled by majority voting because the number of fluctuations is small, and does not affect optimal phase selection.

The 8-bit parallel signal 5 determined by majority vote in this way
6 to 63 are address A of ROM16.

~A7, below ROM16 and multiplexer 1
7.18 operates in the same way as the conventional example described above.

In the above embodiment, the buffer circuits 1 to 7 are used as delay elements in the phase circuit, but any circuit system may be used as long as it can generate an output having a phase different from that of the input. For example, it is possible to use a digital delay line, a capacitor, etc.

Furthermore, in the embodiment, the majority decision circuit is constructed using a four-stage binary counter, but a multiphase clock may be latched for each edge of the C signal (bit synchronization signal), and its output may be determined by a combination of gates.

In the embodiment, the logic level of the multiphase clock is judged using a total of 16 edges of the CR signal (bit synchronization signal), but even if the number of judgments is 15 or less, the noise and other noises are at least lower than in the conventional example. The impact will be less. For example, when making a determination using eight edge pulses, only three stages of binary counters are required, which has the effect of simplifying the circuit configuration.

The ROM 36 has outputs A, B, and C sufficient to select the optimum phase block according to the eight input line data.

A combination circuit of a NAND circuit or a NOR circuit may be used as long as D can be obtained, and in this case, the circuit size can be made smaller than that of a ROM.

〔Effect of the invention〕

According to the present invention, in a synchronous clock generation circuit, when determining a clock with the optimal phase from among multiphase clocks, the determination is made based on the edge timing of the bit synchronization signal multiple times, and a block is selected based on the majority vote of the results. By making the selection, even if the Pitt J'JIM issue includes time axis fluctuations, the degree of interference with correct selection can be reduced.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram showing the general format of a teletext signal, Figure 2 is a circuit diagram showing a conventional synchronous clock generation circuit, and Figure 3 is an example of the waveform of the multiphase four-way signal in Figure 2. FIG. 4 is a circuit diagram showing an embodiment of the present invention. FIG. 4A is a waveform diagram showing signal waveforms of the main parts in FIG. 4. ...Buffer (delay element), 8 to 15.
・・・・・・D type flip 70 knobs, 16・・・・・・I
ILOM (read-only memory), 17, 18...
...Multiplexer, 43...3-man-powered AND gate, 44...4-stage binary counter, 45~
52・・・Latch circuit agent Patent attorney Namiki
Akio

Claims (1)

[Claims] 1) a first means for generating a plurality of sets of clock signals having the same repetition frequency but different phases from a specific clock signal, and receiving a serially transmitted data string and synchronizing with the data string; a second means for detecting a synchronization signal; a third means for latching each ring level of the plurality of sets of logic signals at the detection timing of the synchronization signal; and fourth means for selecting a clock signal having a specific phase relationship with respect to the phase of the synchronization signal from among a plurality of sets of click signals and outputting the selected clock signal as a periodic clock signal. The second means includes means for detecting a synchronization signal synchronized with the data string a plurality of times over a plurality of periods, and the third means detects the plurality of sets of four-way signals at the plurality of detection timings of the synchronization signal. A synchronous clock generation circuit comprising means for examining each logic level multiple times and latching the results of the examination according to the majority rule.