JPS60206352A - Envelope generating circuit - Google Patents

Abstract

PURPOSE:To obtain an envelope generating circuit which can save the power and make the circuit small in size by constituting said circuit of a pulse generating circuit for generating a pulse of a prescribed width at the time of connection of a burst control signal, and a differentiating circuit connected to an output of this pulse generating circuit, and by inserting a diode between the first resistance and a capacitor. CONSTITUTION:A burst control signal of a square wave from an input terminal 1 is inputted to an integration circuit 2. To the integration circuit 2, a diode 10 is connected in the direction for obstructing the discharge of a capacitor 11, and in the output of the integration circuit 2, an integral waveform which rises gently is obtined in accordance with a time constant of c(R+r) determined by a resistance 9 of a resistance value ''R'', the diode 10 of an on-resistance ''r'' and the capacitor 11 of a capacity ''c''. On the other hand, as for a waveform when the burst control signal is off, since the diode 10 is connected in reverse, a discharge time of the capacitor 10 is determined by a resistance variable circuit 3 connected to the output side of the integration circuit 2. Accordingly, a discharge time of a charge accumulated in the capacitor 11 is controlled by control of the resistance variable circuit 3, and an inclination of an envelope can be set to a desired inclination.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to time division multiple access communication (hereinafter referred to as TDM).
A: It's called 1ffl Shin. The present invention relates to a burst envelope generation circuit for performing envelope control of transmission bursts used in the ) method.

[Description of prior art]

In the Tr) MA borrowing method, a phase shift keying modulation method (hereinafter referred to as PSK modulation method) is often used.

In the case of this modulation method, when a 180 degree phase change occurs such as when the phase of the modulated data is 0/π, a gentle constriction occurs in the carrier wave, so burst control is performed by switching at this point. By doing so, the spread spectrum phenomenon caused by carrier switching can be suppressed to a certain extent.

However, when a frequency modulation method (hereinafter referred to as IiM modulation method) is adopted and a carrier wave with a constant envelope is burst isotuned using a square wave, the spectrum spreads as a result of this, causing interference to other channels. In addition to this, there is a possibility that interference between transmitting and receiving may occur in the receiver of the own station. For this reason, when performing TDMA communication using the collective modulation method, it is necessary to control a burst waveform having a gentle rise and fall of l-I/1, as seen in the envelope of the PSK modulation method.

One of the methods of envelope control is to prepare a burst envelope and control it so that it becomes a similar envelope. A digital envelope generation circuit has been used as a conventional circuit for this purpose.

This digital envelope generation circuit sequentially generates 1 by the clock.
? After reading the OM data and converting it into an analog signal using a digital-to-analog converter, filtering is performed to generate a target envelope. However, ICs that generally operate at high speeds (ICs consume a lot of power, are expensive, and may require power supplies with both positive and negative polarities, as well as peripheral circuits such as Lasoji circuits and digital-to-analog converters). Therefore, there are problems such as a large mounting space is required and the circuit becomes large.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an envelope generation circuit which eliminates the above-mentioned drawbacks and which reduces power consumption and miniaturizes the circuit.

[Key points of the invention]

The present invention generates a burst envelope having gentle rising and falling characteristics, and includes a pulse generating circuit that generates a pulse of a predetermined width when a burst control signal is disconnected, and a pulse generating circuit connected to the output of this pulse generating circuit. a differentiating circuit, and an integrating circuit configured by inserting a diode that guides illumination in the direction of the burst control signal between the first resistor and the capacitor, and outputting an output from the connection point between the content 1° and the diode; A variable resistance element whose one end is connected to the output point of this integrating circuit and whose resistance value changes depending on the output signal from the integrator circuit, and a second variable resistance element connected between both terminals of this variable resistance element. The present invention is characterized by comprising a variable resistance circuit including a resistor and a third resistor whose one end is connected to the other end of the variable resistance element and whose other end is connected to a common potential.

[Explanation based on examples]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block configuration diagram showing the configuration of this embodiment circuit, FIG. 2 is a connection diagram showing the configuration of the main blocks constituting this embodiment circuit, and FIG. 3 (7) (1 )
~(IV) is a signal waveform diagram of each part of FIG. 2(7) (+) ~(TV).

First, the configuration of this embodiment circuit will be explained based on FIGS. 1 and 2. This embodiment circuit includes an input terminal 1, an integrating circuit 2, a variable resistance circuit 3, a filtering circuit 4, an output terminal 5, a pulse generating circuit 6, a differentiating circuit 7, and an integrating circuit output terminal 8. configured. Here, the integrating circuit 2 includes an integrating lit resistor 9, a diode 10, and an integrating capacitor 1.
1, the variable resistance circuit 3 is composed of a high resistance 12, a field effect transistor 13, and a low resistance 14,
Further, the differentiating circuit 7 includes a differentiating capacitor 15 and a differentiating resistor 16.

Input terminal 1 is the input of integration circuit 2 and pulse generation circuit 6
The output of the integrating circuit 2 is connected to the integrating circuit output terminal 8, while the output of the pulse generating circuit 6 is connected to the input of the differentiating circuit 7, and the output of the differentiating circuit 7 is connected to the variable resistance circuit. 3, the output of the variable resistance circuit 3 is connected to the integrating circuit output terminal 8, the integrating circuit output terminal 8 is connected to the input of the filtering circuit 4, and the output of the filtering circuit 4 is connected to the output terminal 5. Ru. Here, the input of the integrating circuit 2 is connected to one end of the integrating resistor 9, the other end of the integrating resistor 9 is connected to the anode of the diode 10, and the cathode of the diode 10 is connected to one end of the integrating capacitor 11 and the integrating resistor 9. It is connected to the circuit output terminal 8, and the integrating capacitor 11
The other end of the differential circuit 7 is connected to the Hyogo potential, and the input of the differentiating circuit 7 is connected to one end of the differentiating capacitor 15. Field effect transistor 1 of variable circuit 3
3, and the other end of the differential resistor 16 is connected to the gate of i
In addition, the source of the field effect l transistor 12 of the variable resistance circuit 3 is connected to one end of the low resistance 14 and one end of the high resistance 12, and the other end of the low 11°C resistor 14 is connected to the m potential. are connected to a common potential, and the drain of the field effect transistor 13 is connected to the other end of the high resistance 12 and the integrating circuit output terminal 8.

Next, the operation of this embodiment device will be explained based on FIGS. 1 to 3.

A rectangular wave burst control signal from an input terminal 1 is input to an integrating circuit 2. A diode 1 and 10 are connected to the integrating circuit 2 in a direction that prevents the capacitor 11 from discharging.
The output of the integrating circuit 2 includes a resistor 9 with a resistance value rRJ, a diode 10 with an on-resistance [rl], and a capacitor with a capacitance rcJ.
An integral waveform that rises gently according to the time constant of c (Rlr) determined by Jll is obtained. On the other hand, in the waveform when the burst control signal is off, the diode 10 is reversely connected and therefore the variable resistance circuit 3 connected to the output side of the integrating circuit 2 determines the discharge time of 37774 months.

Therefore, as shown in FIG. 1, the discharge time of the charge accumulated in the capacitor 11 is controlled by controlling the variable resistance circuit 3, and the inclination of the wrapped cotton can be set to a desired inclination. Furthermore, this output waveform is waveform-shaped by the Urahami circuit 4, and a burst envelope output with little change in both rising and falling edges can be obtained.

Here, a depletion type field effect transistor 13 is connected to the output of the integrating circuit 2 as shown in the figure, and one channel is grounded via a low resistance 14. Further, a high resistance 12 is connected between the channels, and a differentiation circuit 7 for generating a differential waveform from the output signal of the pulse generation circuit 6 is connected to the gate of the field effect transistor 13.
is connected.

Therefore, the control signal shown in FIG. 3(1) is applied to the input terminal 1.
, the integration circuit output 8 has a rising output waveform (IV
) is obtained. On the other hand, in the pulse generation circuit 6, the burst control signal is lower than l! A pulse (n) of constant width is created at point T,
Further, in the differentiating circuit 7, a differentiated waveform as shown in (Ill) is created and applied to the gate of the field effect I-transistor 13 as a control signal.

As mentioned above, when the burst control signal is off, the charge accumulated in the capacitor 11 is discharged through the channel of the field effect I transistor 13 because the diode is inserted in the opposite direction, but (Ill) As shown in
During this time period, the gate of the field effect transistor 13 is deeply reverse biased and is therefore in a cutoff state.

In this time interval t1, discharge is performed via the high resistance 12 and the low resistance 14 by a specific number τ.

Day 1 of the field effect transistor 3 - The bias gradually becomes shallower and the potential becomes "0" ■ In the time period [2, the field effect transistor I3 used is a depletion type, so the channel resistance becomes conductive with a certain resistance value. death,
As a result, the discharge effect is accelerated with a time constant of τ2, and the slope becomes even steeper. Furthermore, when a positive pulse shown in (Ill) in the figure is input to the gate of the field effect transistor 13 after the time interval LI+12 has elapsed, the channel resistance becomes even lower, and within the time interval t3, the time constant of τ3 increases. The discharge ends at , and a control waveform shown in (rV) is obtained. This output waveform is shaped by the Urahami circuit 4 and becomes a burst envelope output.

〔Effect of the invention〕

As described above, the present invention generates an envelope using a less expensive circuit and low power consumption, and therefore has the effect of making the apparatus more economical than the conventional apparatus.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a connection diagram showing the configuration of the main parts of FIG. 1. FIG. 3 is a signal waveform diagram showing waveforms at various parts in FIG. 2. 1... Input terminal, 2... Integrating circuit, 3... Resistance variable circuit, 4... Filtering circuit, 5... Output terminal, 6...
・Pulse generating circuit, 7... Differentiating circuit, 8... Integrating circuit output, 9... Integrating resistor, 10... Diode, 1
1... Integrating capacitor, 0 12... High resistance, 13... Field effect 1 transistor,
14...Low resistance, 15...Differential capacitor, 16.
...ffk resistance resistance permit Applicant: NEC Corporation, - Agent: Patent attorney Naoto Ide 1 Figure 1 Figure 2

Claims (1)

[Claims] (1) Hurst connection between a pulse generation circuit that generates a pulse of a predetermined width when the burst control signal is interrupted, a differentiator circuit connected to the output of this pulse generation circuit, and the first resistor and capacitor. It is constructed by inserting a diode 1, which conducts in the direction of the signal, and an integrating circuit which outputs from the connection point of this capacitor and this diode, and one end of which is connected to the output point of this integrating circuit, and outputs from the differentiating circuit. to the output signal. A variable resistance element whose resistance value changes by 1 mm, a second resistor connected between both terminals of this variable resistance element, one end of which is connected to the other end of this variable resistance element, and the other end connected to a common potential. an envelope generating circuit comprising: a variable resistance circuit comprising a third resistor connected thereto;