JPS6020774B2 - Serial parallel converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a serial-to-parallel converter used in remote monitoring and control equipment, etc., in which the function of converting a serial code into a parallel code is performed by program control.

Regarding centralized control of power generation and substations, it is necessary to handle a huge amount of information. Moreover, currently used information transmission devices such as COT and remote monitoring and control devices are realized with various encoding systems, transmission formats, and transmission speeds, and a huge amount of hardware is required to handle them all at once. becomes. Incidentally, conventionally, a serial-to-parallel converter (hereinafter referred to as an SP converter) used in a remote monitoring control device or the like is constructed of wire logic, LSI, programmable logic, or the like.

However, both of these methods are realized on the assumption that the transmission format and transmission coding system are fixed, and even if the system is controlled by a relatively flexible program, if the coding system differs, hardware changes are required. Although the speed was based on wired logic, the minimum speed was the limit. Furthermore, when attempting to centrally monitor and control remote monitoring and control equipment and information transmission equipment that have different transmission methods (transmission code systems, transmission formats) as described above, the equipment is implemented using different hardware for each transmission method. If such a system were to be implemented, a huge burden would be placed on implementation costs and maintenance management. Furthermore, since conventional SP converters are realized with a register length of at least half a length, that is, 20 to 32 bits, the number of control circuits is large. It was the most complex circuit module in remote monitoring and control equipment. Therefore, the present invention is applicable to all transmission methods used in such systems as well as conventional small-scale systems, and the hardware is significantly simplified to improve reliability, margin, and processing speed. The purpose of the present invention is to provide a serial-to-parallel converter that can significantly improve the performance. An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block circuit example of the configuration of an SP converter according to the present invention.

In FIG. 1, 1 is a demodulator that converts a modulated signal into pulses, 2 is a level converter used when the voltage level of the demodulated signal is different, and 3 is a gate controller that controls the gate of an SP register (described later), which controls shift pulses and pulses. This is a timing control that generates a ready signal. Also 4
is an SP register that converts a serial input signal to a parallel signal,
This SP register 4 has a register length shorter than 40 to 64 bits for one word of the normally used transmission format shown in FIG. It is configured. 5 is an output register that outputs the parallel converted signal to an external device; 6
A flip-flop outputs a ready signal indicating that data is prepared in the output register 5, and a microprocessor (MPU) 7 inputs the output of the output register 4 to perform signal error checking and synchronization determination.

Next, the operation of the apparatus constructed as described above will be explained with reference to the time chart shown in FIG.

First, the signal LP in FIG. 3 that has passed through the demodulator 1 is converted into a serial pulse code, and if necessary, a level converter 2 is used.
The signal is input to the SP register 4 via the . At the center of each bit of this signal LP, the timing controller 3
A shift pulse SEP shown in FIG. 3 is generated which is output to the register 4, and the SP registers are sequentially shifted. The bit counter in the timing controller 3 is B in Fig. 3.
As shown in C, when the 8th bit is counted and reaches "7", the ready output flip-flop 6 is first reset by the RDY signal in FIG. 3, and then the contents of the SP register 4 are reset. In other words, T in Figure 3
The P signal is transferred to the output register 5, and then the ready flip-flop 6 is set. This ready flip-flop 6 is reset again by a read signal MR shown in FIG.
Focusing only on the ready flip-flop 6, when data is first prepared in the output register 5, it is set by the timing roller 3, the contents of the output register 5 are taken in by the M circle U7 and reset, and the next new 8 The bit is written to the output register 5 and set again. This type of automatic operation is currently used in conventional computer input because it prevents erroneous data from being input, but as in the present invention, programmable logic is directly integrated with hardware logic. When the device is configured, a ready signal is sent to the output register 5 to drop the ready state. In other words, the reason why one data is prevented from being read once or more than a set number of times is due to the sequence of repeatedly writing the contents of the output register 5 in short cycles by interrupt processing. This is an essential function in order to avoid complexity and a reduction in the overall processing speed of the device due to the measures added to deal with this complexity. In addition, abnormalities in the SP converter operation can be checked directly by the MPU 7 based on the operating state of the ready signal. For example, if the ready value does not change for a long time, it can be clearly determined that there is an abnormality in the SP converter. Therefore, an SP converter having such a configuration can be commonly applied to all transmission formats such as the equal length code system and the long/short code system currently in use. Next, operations corresponding to each encoding system and transmission format will be explained in sequence. M
The number of parallel processing bits of the PU 7 may be 4, 8, 12, 1 blind, etc., but below, the case of 8 bits will be described as an example. The currently used encoding system is shown in Figure 4. In the equal length code, the pulses representing "1" or "0" are equal, and in the long/short code, the pulses representing "1" and "0" are different. If the longer one is "1", the shorter one is "0".

The difference between NRZ and RZ is that in RZ, “0” is always inserted between 1-bit signals to distinguish each bit, whereas in NR
This is not the case with Z. In the case of {1} (NRZ) equal length code, when the 8th bit of SP register 4 is shifted, the next 9th bit is shifted.
By the time the bit is shifted, the contents of the SP register 4 are transferred to the output register 5.

At this point, the ready flip-flop 6 (hereinafter referred to as F/F) is set, the MPU 7 confirms the readiness, and the contents of the output register 5 are taken into the memory. Here, the ready F/F 6 is reset by the read signal from the output register 5. By repeating the procedure, every 8 bits are taken into memory. In this case, in a conventional SP converter that is composed entirely of hardware, a dedicated hardware logic for detecting a synchronization word is provided, but this device is not provided with this hardware. This is because the synchronization word itself generally has a special bit configuration, and it changes significantly depending on each transmission format, so providing dedicated hardware is advantageous in terms of processing speed, but it is not suitable for each transmission format. This is extremely disadvantageous in terms of flexibility and hardware simplification. Therefore, in this device, all processing is performed by stored logic (stored in ROM). That is, the pattern of the synchronization word is determined and confirmed from among the data taken every 8 bits, and the starting bit position of the transmission word is determined. Since this sequence is programmable, it is easy to change it according to the encoding system and transmission format. Furthermore, the processing time is no problem since it is only a matter of checking the synchronization word pattern. Once the synchronization word is confirmed using the above procedure, the data taken in every 8 bits is edited word by word. Therefore, if the bit length of one word differs depending on the transmission format, this part of the processing can be handled simply by pointing to the bit length. ■
In the case of (RZ) equal length code In this case, there is always a low level ``0'') between each bit of the (NRZ) equal length code, so the processing is 1
The other processing is exactly the same except that the word bit length is twice that of the (NRZ) equal-length code.

In the case of '31 (NRZ) long/short codes In the case of (NRZ) long/short codes, the precision during signal pulse time is slightly lower than the characteristics of conventional hardware, so long codes and short codes can be clearly distinguished as the difference in bits. The timing is set as follows, and the input signal is shifted to the SP register 4 at this timing.

For example, in the case of a 2:1 long/short code, if you shift it to the SP register 4 during a pulse that is one-third of the short code, the long code will always be in the range of 5 to 7 bits, and the short code will be in the range of 2 to 4 bits. This becomes a pattern of consecutive "1"s or "0"s. Therefore, the bit length of the same code is counted by the stored logic to determine whether the signal is "1" or "0". Although the processing speed of this method is clearly lower than that of equal-length codes, the transmission speed of long/short codes using conventional equipment is generally less than a fraction of that of equal-length codes due to hardware constraints. Therefore, the above processing is sufficient. In order to further improve efficiency, if a shift pulse is generated for about half the time of the pulse of the short code based on the signal change point and shifted to the SP register 4, the short code is 1 bit, and the long code is 1 bit. Since 2 bits of consecutive "1" or "0" are lined up, the long/short code can be determined by this. However, the latter requires some additional hardware. ■ In the case of (RZ) long/short code In this case, compared to the (NRZ) long/short code, there is always a low level (“0”) between 1-bit signals, so this is the same as the short code. Everything is the same except that it is imported into .

As is clear from the above explanation, the above four-code system can be handled without changing the hardware.

It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, but can be similarly implemented with the following modifications. i) As mentioned above, the parallel processing bit is 4 other than 8 bits.
, 12, or 16 bits, the register lengths of the SP register 4 and the output register 5 may be changed, and the timing controller 3 may be set to match the respective register lengths. ii) When most of the processing of the MPU 7 is the discussion of the output register 5, or when the transmission speed of a remote monitoring control layer, etc. is slow, the same signal as the ready signal can be used as an interrupt input to the MPU 7. The interrupt may be canceled at the same time as the output register 5 is read. ii
D When there are two or more SP converters for one MPU 7, the SP converter of the present invention is provided for the necessary number of channels, and the contents of each output register are sequentially reduced, and the MPU side converts each channel separately. Multi-channel parallel processing may be used. Even in this case, everything is basically the same, and almost no externally added circuitry is required. As described above, according to the present invention, the microp. It can be applied to all transmission methods used in conventional remote monitoring and control equipment, etc., and the hardware is significantly simpler and more reliable than conventional SP converters. performance and tolerance can be greatly improved. In addition, in the SP converter, the longer the register length, the more complicated the hardware becomes, and the shorter the register length, the more complex the processing sequence becomes and the longer the processing time is required. Therefore, in the conventional program-controlled bit-by-bit processing, the speed was limited and was limited to the lowest speed by hardware, but in the present invention, by providing a register for the number of parallel processing bits of the MPU, the hardware This has the effect of increasing processing speed while maintaining simplicity and flexibility in changing transmission formats.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the SP converter of the present invention, and FIG. 2 is a 1 word 44
FIG. 3 is a time chart showing the operation of this embodiment. FIG. 4 is a time chart explaining each coding system. 1... Demodulator, 2... Level converter, 3. ...Timing controller, 4...SP register, 5...Output register, 6...Ready F/F
, 7...Microprocessor (M circle U). Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a serial-to-parallel conversion device used in a remote monitoring control device, etc., which includes a signal transmission device that transmits and receives information, an information processing control device that processes the information, and an input/output device for external equipment, the information processing control device a conversion register which has a relatively short register length corresponding to the number of parallel processing bits of the microprocessor and which sequentially takes in the serial pulse codes demodulated by the signal transmission device and converts them into parallel codes; a timing controller that receives a demodulated serial pulse code and sequentially outputs a shift pulse to the conversion register at the center of each bit representing the code and generates a ready signal when the final bit is counted; an output register that transfers the contents and outputs the data; and an output register that is reset by a ready signal generated from the timing controller and is set when data is prepared in the output register, and the data of the output register is transferred by the information processing control device. and a ready memory circuit that is reset again by a read signal from the information processing control device when the data is taken in, and when the information processing device takes in the data of the output register, the data is stored in a pre-stored logic sequence. 1. A serial-to-parallel conversion device that is capable of handling different transmission methods by performing logical operations based on the base.