JPH04200119A - Parallel-serial parallelization device - Google Patents

Abstract

PURPOSE:To attain parallel - serial conversion independently of a bit number of a data bus by comparing a setting value calculated by a sequencer with a coefficient of a count means, discriminating the end of parallel - serial conversion and informing the result of discrimination to the sequencer. CONSTITUTION:A comparator 4 compares a setting value set by a sequencer 1 with a count of a counter 5 and when they are coincident, it is discriminated that the parallel - serial conversion of a data in a prescribed bit number is finished as one block and a coincidence signal CD is outputted. The counter 5 counts a bit number of the said data as one block. An AND circuit 6 gives an AND between a shift register selection signal SR from the sequencer 1 and the said coincidence signal CD to shift registers 3a, 3b. A synchronization circuit 7 outputs a conversion end signal TF based on the coincidence signal CD and informs it to the sequencer 1 that the parallel - serial conversion of the data in processing bit number is finished as one block.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention is applicable to parallel
This invention relates to a serial conversion device.

BACKGROUND OF THE INVENTION In recent years, parallel-to-serial converters that are capable of high-speed conversion and have simple configurations have become mainstream.

Conventionally, this type of parallel-to-serial converter was developed in
The configuration disclosed in Publication No. 38 was common.

That is, as shown in FIG. 4, n input devices 31a to 31n
and one parallel-to-serial converter 32, and the parallel-to-serial converter 32 has a function of converting m-bit parallel data to serial data and outputting the same, and also has the function of converting m-bit parallel data to serial data and outputting it, and also The conversion end signal a is input to the input device 312~
31n, and a function of outputting a selection signal to the input device 31a when transmitting the first word (synchronization word). When the input device 31a receives the selection signal S from the parallel-serial converter 32, it outputs m-bit parallel data C to the m-bit data buses 33a to 33m in synchronization with the timing of the conversion end signal a. do. When the input device 31b receives the selection signal d from the input device 31a, it outputs m-bit parallel data e to the m-bit data buses 33a to 33m in synchronization with the timing of the conversion end signal a. Similarly, when the input device 31n at the final stage receives the selection signal, the m-bit parallel data f is transferred to the m-bit data areas 33a to 33a in synchronization with the timing of the conversion end signal a.
Output to 33m.

In this way, the selection operation of the input devices 31a to 31n reaches the final stage input device 31n, and this final stage input device 31n
The next input device selection signal g is output to the parallel-to-serial converter 32.

When the parallel-to-serial converter 32 completes the parallel-to-serial conversion of the parallel data f from the input device 31n at the final stage, it reads the timing selection signal in synchronization with the conversion end signal a and enters the initial state. Continue repeating the action.

Problems to be Solved by the Invention However, in such a conventional parallel-to-serial converter, the number of bits of parallel data to be converted is limited to the data bus 33.
The circuit is configured so that the number of bits from a to 33m is an integer multiple, and the data bus 3, such as 1 bit or 2 bits, is
There were problems in that it was not possible to transfer a number of bits less than 33 to 33m bits, and it was not possible to arbitrarily change the number of bits of parallel data to be converted.

The fact that it is not possible to transfer a number of bits less than the number of bits of the data buses 33a to 33m or to arbitrarily change the number of bits of parallel data to be converted in this way poses a problem in the following cases, for example. That is, in a hard disk drive device, as a method for recording servo information, there is an embedded servo method in which data information and servo information are mixed on one disk. FIG. 5 shows how the disk surface is formed using the embedded servo method. When formatting with the embedded servo method, servo information and data information are converted into parallel-to-serial bits corresponding to the amount of information, the servo information is written to the servo area 41 on the disk surface, and the data information is written to the disk surface. Upper data area 4
Write in 2.

Now, if the focus number of servo information is 100 bits,
For an 8-bit data bus, 100/8=12...4 bits remain. In other words, if data is transferred to the data bus 12 times, 4 bits remain. Similarly, for a 16-bit data bus, 100/16=6...4 bits remain.

Conventional parallel-to-serial converter configurations do not have a control circuit to transfer these extra bits, and the problem is that transfer is not possible unless the amount of servo information is an integral multiple of the number of bits on the data bus. there were.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a parallel-to-serial conversion device that can perform parallel-to-serial conversion without being limited by the number of bits of a data bus.

Means for Solving the Problems The present invention includes a sequencer that controls parallel-to-serial conversion, a storage unit that stores parallel data transferred from the sequencer, and a storage unit that reads the parallel data stored in the storage unit and converts it into serial data. a parallel-to-serial conversion means for converting the data into serial data; a counting means for counting the number of bits of the serial data converted by the parallel-to-serial conversion means; a comparison means for comparing the set value calculated by the above with the counted value of the counting means to determine that parallel-to-serial conversion of data of a prescribed number of bits has been completed; and a comparison means for transmitting the determination result of the comparison means to the sequencer It is characterized by having a synchronization means for transmitting the information.

Operation In the present invention, the storage means stores parallel data transferred from the sequencer. Then, the parallel-to-serial conversion means reads the parallel data stored in the storage means and converts it into serial data. Then, the counting means counts the number of bits of the serial data converted by the parallel-to-serial converting means. Then, the comparing means compares the set value calculated by the sequencer in correspondence with the number of bits of the data to be converted by the parallel-serial means with the count value of the counting means, and converts the data of the specified number of bits into parallel-serial data. Determine when conversion is complete. Then, the synchronization means transmits the determination result of the comparison means to the sequencer. Therefore, data whose number of bits does not correspond to an integral multiple of the number of bits of the data bus can be converted from parallel to serial.

EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 to 3.

FIG. 1 is a circuit block diagram of a parallel-to-serial conversion device according to an embodiment of the present invention. This parallel-to-serial conversion device includes a sequencer 1 and four registers 2a to 2 as storage means.
d, four shift registers 3a to 3d as parallel-to-serial conversion means, a comparator 4 as comparison means, a counter 5 as counting means, an AND circuit 6, and a synchronization circuit 7 as synchronization means. , and an OR circuit 8. Sequencer 1 controls parallel-to-serial conversion, and receives register selection signals R3EL1 and R3E.
L2 is output to registers 2a and 2b.

Parallel data is transferred to 2c and 2d, and a register selection signal R3EL3 is output to set the number of bits of data to be converted from parallel to serial as one block in the comparator 4. Shift registers 3a, 3b, 3c, and 3d are connected to each other in series, and serial data is output from shift register 3a. A shift register 3a is connected to the register 2a, a shift register 3b is connected to the register 2b, a shift register 3C is connected to the register 2C, and a shift register 3d is connected to the register 2d.
, 2b, 2c, and 2d are converted into serial data by shift registers 3a, 3b, 3c, and 3d. The comparator 4 compares the set value set by the sequencer 1 and the count value of the counter 5, and when they match, it is determined that the parallel-to-serial conversion of data of a predetermined number of bits as one block has been completed. It makes a judgment and outputs a coincidence signal CD. The counter 5 counts the number of bits of data converted from parallel to serial as one block. The AND circuit 6 supplies the AND of the shift register selection signal SR from the sequencer 1 and the match signal CD from the comparator 4 to the shift registers 3a and 3b. Synchronous circuit 7
outputs a conversion end signal TF based on the coincidence signal CD from the comparator 4, and notifies the sequencer 1 that parallel-to-serial conversion of data of a predetermined number of bits as one block has been completed. The OR circuit 8 receives the register selection signal PSELI from the sequencer 1.

2 and the reset signal R3 is supplied to the counter 5 and the synchronization circuit 7.

Next, the operation will be explained. The number of bits of the data bus is 16 bits, registers 2a to 2d, shift registers 3a to 3d,
The number of bits of comparator 4 and counter 5 is 8 each.
Bit. Register selection signal PS from sequencer 1
When ELI is output, the data bus values are latched in registers 2a and 2b, and when register selection signal R3EL2 is output from sequencer 1, registers 2c and 2d are latched.
The value of the data bus is latched. When the register selection signal R3EL3 is output from the sequencer 1, the value of the data bus is latched into the comparator 4 as a set value. Furthermore, when the match signal CD output from the comparator 4 is at a high level and the shift register selection signal SR output from the sequencer 1 is at a high level, the shift registers 3a, 3b, 3c, 3
d is loaded with parallel data from registers 2a, 2b, 2c, and 2d, and a match signal C is output from comparator 4.
When D is at high level and shift register selection signal SR output from sequencer l is at low level, parallel data is loaded from registers 2c and 2d into shift registers 3c and 3d in synchronization with clock signal CK. .

When the conversion of a predetermined number of bits of data as one block is completed, the synchronization circuit 7 sets the conversion end signal TF to a high level, and the counter 5 is reset.

In addition, the sequencer 1 registers 2a, 2b, 2c
, 2d, or outputs the reset signal R3, the synchronization circuit 7 sets the conversion end signal TF to a low level.

The shift registers 3a to 3d, the counter 5, and the synchronization circuit 7 have a common clock for parallel-to-serial conversion.

A clock signal CK is input, and the conversion speed of parallel-to-serial conversion is uniquely determined by this clock signal CK.

Here, the normal parallel-to-serial conversion operation will be explained in detail with reference to the timing chart of FIG. First, the register selection signal R3EL1. R3
EL2. R3EL3 is output. By this register selection signal PSEL1, 16-bit parallel data DnO-15 to be converted into serial data is transferred from the sequencer 1 to the register 2a.

2b and is latched, register selection signal R3E
By L2, 16-bit parallel data Dn16-31
is supplied from the sequencer 1 to the registers 2c and 2d and latched, and by the register selection signal R3EL3, 16
A set value of ``Of'' in base numbers is supplied from the sequencer 1 to the comparator 4 and launched.

Then, when sequencer 1 outputs reset signal R3,
The counter 5 starts counting the clock signal CK from the initial value "oo", and the synchronization circuit 7 sets the conversion end signal TF to a low level.

When the 16th clock signal CK15 is input to the counter 5, the count value of the counter 5 becomes "off", and the comparator 4 outputs the coincidence signal CD. This coincidence signal CD
is input to the shift registers 3a to 3d when the shift register selection signal SR from the sequencer is at high level, and the 32-bit parallel data DnO to 3 of the registers 2a to 2d are inputted to the shift registers 3a to 3d at the timing of the 17th clock signal CK16.
I is loaded into shift registers 3a-3d.

Further, the coincidence signal CD is input to the synchronization circuit 7, and the synchronization circuit 7 thereby sets the conversion end signal TF to a high level at the timing of the clock signal CK. Further, the coincidence signal CD is input to the counter 5, whereby the counter 5 is reset to the initial value "00" at the timing of the clock signal CK.

At a predetermined timing after the conversion end signal TF becomes high level, the sequencer 1 writes 16 to the registers 2c and 2d.
Bisoto parallel data Dn32 to Dn47 are stored, and the conversion end signal TF from the synchronization circuit 7 is set to low level. During this time, the shift registers 3a to 3d receive the clock signal CK.
The 32-bit data DnO to DnO-31 are sequentially shifted and converted into serial data at the timing of .

When the count value of the counter 5 becomes "Off" again, the conversion of the 16-bit parallel data DnO-15 to serial data is completed, and the 16-bit parallel data Dn16-31 is shifted to the shift registers 3a and 3b. synchronous circuit 7
The conversion end signal TF from 1 to 2 becomes high level. Furthermore, since the shift register selection signal SR from the sequencer 1 is at a low level, the match signal CD is output from the comparator 4, so that the 16-bit/7-bit parallel data Dn32 to 47 stored in the registers 2c and 2d is is loaded into shift registers 3c and 3d.

In this manner, when converting parallel data proportional to the number of focuses on the data bus into serial data, the above operation is repeated, and 16-bit data is continuously converted as one block.

Next, the operation of parallel-to-serial conversion of parallel data whose number of bits is less than or equal to the number of bits of the data bus will be described in detail with reference to the timing chart of FIG. If the number of bits of parallel data to be converted is 2 bits, 16 bits +
It is treated as 2-bit parallel data and parallel-to-serial conversion is performed.

First, when the conversion end signal TF from the synchronization circuit 7 is at high level, the sequencer 1 selects the shift register selection signal SR.
is set to a high level, and the set value "11" is supplied to the comparator 4 to latch it. Thereafter, at a predetermined timing, the sequencer 1 supplies 16-bit parallel data DnO-15 to the registers 2a and 2b to launch them, and also causes the conversion end signal TF from the synchronization circuit 7 to go low.

After that, the sequencer 1 stores 2-bit parallel data Dn! in the register 2c. 6 to 17 for lunch.

When the shift registers 3a to 3d complete parallel-to-serial conversion of 32-bit data, the comparator 4 outputs a match signal C.
D, 18-bit parallel data DnO~17 is loaded from the registers 2a~2C to the shift registers 3a~3C, the power counter 5 is reset to the initial value "00", and the synchronous circuit 7 The conversion end signal TF from 1 to 2 becomes high level.

After that, the sequencer 1 sets the conversion end signal TF from the synchronous circuit 7 to low level, and when the serial conversion of the 18-bit parallel data is completed, the conversion end signal TF from the synchronous circuit 7 is set to low level.
changes to high level to notify the sequencer 1 of the completion of parallel-to-serial conversion.

In this way, while the shift registers 3a to 3d are performing parallel-to-serial conversion, the sequencer 1 sets the parallel data, the number of bits of data to be converted, and the synchronization circuit 7.
Therefore, parallel-to-serial conversion is possible even for bi-count data that does not correspond to an integral multiple of the number of bits of the data bus, and parallel-to-serial conversion operations can be performed continuously.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described above, there is provided a sequencer for controlling parallel-to-serial conversion, a storage means for storing parallel data transferred from the sequencer, and a storage means for reading the parallel data stored in the storage means. a parallel-to-serial conversion means for converting the data into serial data; a counting means for counting the number of bits of the serial data converted by the parallel-to-serial conversion means; comparing means for comparing the set value calculated by the sequencer with the counted value of the counting means to determine that parallel-to-serial conversion of data of a prescribed number of bits has been completed; Since the sequencer is provided with synchronization means for transmitting information to the sequencer, while the shift register is performing parallel-to-serial conversion, the sequencer can set parallel data, set the number of bits of data to be converted, and control the synchronization circuit. As a result, it is possible to perform parallel-to-serial conversion even on data whose number of focuses does not correspond to an integral multiple of the number of bits of the data bus, and moreover, it has an excellent effect that the parallel-to-serial conversion operation can be performed continuously.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a parallel-to-serial converter according to an embodiment of the present invention, and FIGS. 2 and 3 are timing charts illustrating the operation of the same parallel-to-serial converter, respectively.
Figure 4 is a circuit block diagram of a conventional parallel-to-serial converter.
FIG. 5 is an explanatory diagram of the formant state of a hard disk employing the embedded servo system. 1- Sequencer, 2 a to 2 d- registers (note t
a means), 3a to 3d-shift register (parallel-serial conversion means'), 4-comparator (comparison means), 5-counter (counting means), 7-synchronous circuit (synchronization means). Agent Patent Attorney Tsukasa Nakajima Figure 4

Claims (1)

[Claims] (1) A sequencer that controls parallel-serial conversion, a storage device that stores parallel data transferred from the sequencer, and a parallel-serial conversion device that reads the parallel data stored in the storage device and converts it into serial data. and counting means for counting the number of bits of the serial data converted by the parallel-to-serial conversion means; a set value calculated by the sequencer in correspondence with the number of bits of the data to be converted by the parallel-to-serial means; Comparing means for comparing the counted value of the counting means to determine that parallel-to-serial conversion of data of a prescribed number of bits has been completed, and synchronizing means for transmitting the determination result of the comparing means to the sequencer. A parallel-to-serial conversion device characterized by: