JPS60211978A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor technology, and relates to a technology effective for use in forming bipolar transistors in semiconductor integrated circuits, for example.

[Background Art] The general method of forming bipolar transistors in conventional bipolar integrated circuits and their structures are described in, for example, Nikkei Electronics September 28, 1981 (No. 274').
), page 122, etc. FIG. 1 shows an example of the structure of such a known bipolar transistor.

That is, a bipolar transistor is manufactured by forming an oxide film on a semiconductor substrate 1 made of P-type silicon, and then drilling a hole in the oxide film at an appropriate position to form a buried diffusion pattern.
Using this oxide film as a mask, an N-type impurity such as arsenic or antimony is thermally diffused to partially form an N++-containing layer 2.

Then, after removing the oxide film, a P+ type diffusion layer 3 for a channel stopper is formed, and an N- type epitaxial layer 4 is grown on it by vapor phase growth, and an oxide film (SiO2) is formed on its surface. A nitride film (S i 3 N4) is formed. Thereafter, the oxide film and nitride film are partially removed by photoetching, and using this as a mask, a relatively thick oxide film 5 for isolation is formed in that part, and then the nitride film is removed.

Then, masking with a nitride film or the like, selective thermal diffusion treatment of N-type impurities such as phosphorus is performed on the part that will become the pull-up port of the collector region to form an N+ type scattered layer 6, and also on the N- type epitaxial layer 4. Similarly, a P-type base region 7 is formed by selective thermal diffusion treatment, and an N++ emitter region 8 is formed within this P-type base region 7 by selective thermal diffusion treatment, thereby forming an NPN as shown in FIG. A type of bipolar 1 to transistor was formed.

However, in the bipolar transistor having the above structure, the region that substantially operates as a transistor is only the emitter 8 shown by the chain line A in FIG. 1 and the portion below the emitter 8.

Nevertheless, as shown in the figure, the external base region 8a that brings the base extraction electrode into contact with the emitter region and the collector pull-up port 6 are formed on the outside of the emitter region, so the overall area occupied by the transistor is unnecessarily large. This is a factor that significantly lowers the degree of In addition, since the base region 8 and collector region (pulling port 6 and N++-containing layer 2) are quite thick, the base resistance, base-collector junction capacitance C1°, and collector-substrate junction capacitance CT3 are large. The operating speed was also slow.

Furthermore, as shown in FIG. 1, in a structure in which devices are separated by a thick thermal oxide film 5 formed on the main surface of the substrate, a bird's beak is formed at the edge of the oxide film 5, so the transistor It is clear that the area of the transistor increases and the degree of integration decreases, and when the channel stopper region 3 formed under the oxide film 5 is considered, the degree of integration of the transistor becomes even lower.

[Objective of the Invention] An object of the present invention is to provide a semiconductor technology that can form an ideal transistor with a small footprint and high integration in a semiconductor integrated circuit device, and which has high performance.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, an insulating film and a conductive layer are alternately formed in a sandwich-like manner on the main surface of a semiconductor substrate, a hole is formed through these layers, and an active layer such as single crystal silicon is formed in this hole. By forming a semiconductor and diffusing appropriate impurities from the surface and the conductive layer between the substrate or the insulating films stacked on the substrate into the semiconductor in the hole to form a diffusion layer that will become an active region. The present invention achieves the above object of configuring a transistor with high performance and high integration by reducing the occupied area and junction capacitance.

[Embodiment 1] FIGS. 2 to 8 show an embodiment in which the present invention is applied to a bipolar integrated circuit in the order of manufacturing steps.

In this embodiment, although not particularly limited, first, a semiconductor substrate 1 such as P-type silicon is selectively formed with an N+ type scattering layer 12 by thermal diffusion or ion implantation, and a P+ type scattering layer 12 is formed on the outside thereof to serve as a channel stopper layer. After forming the diffusion layer 3, an oxide film (SiO2) is formed on the surface of the substrate 1 by thermal oxidation.
A first-layer insulating film 14 made of a film) or the like is formed, and a first-layer conductive layer 15 made of polysilicon (polycrystalline silicon) or metal silicide (a compound of metal and silicon) is deposited thereon. Figure 2).

Then, the unnecessary parts of the conductive layer 1 are etched by photo-etching.
5 is removed and an electrode 15a which will later be used for extracting the collector is formed so as to broadly cover the upper part of the N+ type scattering layer 2, and then an oxide film (SiC2) or a nitride film (Si3N4) is formed on the electrode 15a. CVD the second layer insulating film 16 consisting of etc.
A second conductive layer 17 made of polysilicon, metal silicide, or the like is further formed thereon (FIG. 3).

Next, unnecessary portions of the second conductive layer 17 are removed by photoetching, and the collector lead-out electrode 15 is removed.
After forming an electrode 17'a, which will later be used for base extraction, so as to overlap a part of the electrode 17'a, a third layer insulating film 18 is deposited thereon by the same CVD method (Fig. 4). ).

Thereafter, the substrate surface is formed above the N+ type scattering layer 2 by penetrating through the first to third layer insulating films 14, 16, 18 and the first and second layer extraction electrodes 15a, 17a. After forming a through-hole 19 reaching . . . , a polysilicon layer 20 lightly doped with an N-type impurity is deposited thickly over the entire surface of the insulating film 18 by the CVD method (FIG. 5).

Then, etch back is performed to etch the polysilicon layer 20 on the insulating film 18 and planarize it so that the polysilicon remains in the through hole 19. Thereafter, the polysilicon in the through hole 19 is irradiated with a laser and annealed to single-crystallize the polysilicon in the through-hole 19 to form N-type single-crystal silicon 21. Then, when heat treatment is performed, N-type impurities are diffused from the N+ type diffused layer 12 on the substrate into the single crystal silicon 21, and an N+ diffusion layer 2 which becomes a collector region is formed under the single crystal silicon 21.
2 is formed. At this time, by appropriately setting the heat treatment time, as shown in FIG. It can be diffused.

Next, non-doped polysilicon (polysilicon not doped with impurities) 23 is deposited on the single crystal silicon 21 and insulating film 18 in the through hole 19, and then boron is first deposited on this non-doped polysilicon 23. Heat treatment is performed after implanting P-type impurities such as.

Then, a P+ type diffusion layer 24 which becomes a base region is formed by diffusion from this polysilicon 23, and this P+ type diffusion layer 24 is brought into contact with the second layer extraction electrode 17a (
Figure 7).

Therefore, next, an N type impurity such as arsenic is implanted into the polysilicon 23, and then heat treatment is performed to form an N+ type scattered layer 25 which will become an emitter region by diffusion from the polysilicon 13. Thereafter, unnecessary portions of polysilicon 23 are removed by photoetching to form emitter polysilicon electrode 23a.

Then, a contact hole 28a for the collector extraction electrode 15a and the base extraction electrode 17a is provided.
, 28b are formed, resulting in the state shown in FIG. After the state shown in FIG. 8, aluminum is deposited on the entire surface of the insulating film 18, and then aluminum electrodes for the base, emitter, and collector are formed by photoetching to complete the process.

According to the structure of the bipolar transistor as in the above embodiment, the N+ type scattering layer 25P+ type diffusion layer 24. A vertical NPN transistor is formed by using the N- type single crystal silicon region 21a and the N++ diffused layer 22 as an emitter, a base, and a collector, respectively. Therefore, each diffusion layer in the through hole 19 can all substantially contribute to the transistor operation, and as in the transistor with the structure shown in FIG. There is no need for a collector pull-up port, and the emitter size is the same as that of a transistor.

This significantly reduces the area occupied by the transistor and reduces the junction capacitance between the base and collector. The junction capacitance CT8 between the collector and the substrate becomes extremely small, and the base resistance is also minimized. Moreover, the external base extraction electrode 17a and the collector extraction electrode 15
Since a is surrounded by a relatively thick insulating film, the parasitic capacitance outside the element region is also small. As a result, the operating speed of the transistor is significantly improved.

In addition, in the above embodiment, the N++ which becomes the collector region due to the rise of the N+ type scattering layer 12 on the main surface of the substrate.
The height of the diffused layer 22 and the P+ type diffused layer 2 which becomes the base region
By appropriately controlling the depth of the polysilicon 20 filled in the through hole 19 and appropriately setting the concentration of the polysilicon 20 filled in the through hole 19, the N-type single crystal, which is the most important factor influencing the fT of the transistor The thickness and concentration of the silicon region 21a can be respectively optimized. moreover,
In the above embodiment, a P+ type diffusion layer 24 serving as a base region and an N+ type scattering layer 25 serving as an emitter region are formed by diffusion from the polysilicon electrode 23a formed on the single crystal silicon 21 in the through hole 19. As a result, very shallow base and emitter regions are formed.

As a result, according to the above embodiment, fA is high, ultra-high speed,
A high-performance bipolar transistor can be obtained.

Note that the method for manufacturing a transistor with the above structure is as follows:
The present invention is not limited to the above embodiments. For example, in the above embodiment, the N+ type diffusion JW12 formed in advance on the main surface of the substrate
The N type impurity inside is diffused into the lower part of the polysilicon 20 filled in the through hole 19 to form an N++ collector region.
Although a diffused layer 22 is formed, an insulating film 14,
16.18 and conductive layer 15.17 are laminated, a through hole 19 passing through them is formed, and ions are implanted into the main surface of the substrate exposed in the through hole 19 to form an N+ type scattered layer. 12 may be formed, and by diffusion of the N+ type scattering layer 12 and the like, an N++ scattering layer 22 serving as a collector region may be formed.

Furthermore, in the embodiment, the single crystal silicon in the through hole 19 is
The polysilicon filled here is formed by laser annealing, but the through hole 19 is formed by vapor phase growth.
It may also be formed by selectively epitaxially growing single crystal silicon within.

Further, in the above embodiment, the collector lead electrode 15a and the base lead electrode 1 are formed by the conductive layers 15 and 17, respectively.
7a, the first conductive layer 15 or the second conductive layer 17 is formed in an appropriate pattern so that it can also be used as wiring for connecting to other elements formed on the same substrate. You can do it like this.

Furthermore, in the above embodiment, the P+ type diffusion layer 24 serving as the base region and the N type diffusion layer 25 serving as the emitter region are formed by impurity diffusion from the polysilicon 23 formed thereon. It can also be formed by ion implantation.

In that case, the emitter polysilicon electrode 23a may be omitted.

Furthermore, in the above embodiment, a case has been described in which an NPN type bipolar 1 helangister is formed in the single crystal silicon in the through hole 19, but by the same method,
A vertical high performance PNP transistor can be formed in the single crystal silicon within the through hole 19. Moreover, with just a slight increase in the ion implantation process, NPNI-
It is also possible to form transistors and PNP transistors. Furthermore, a resistance made of a diffusion layer can be formed in the silicon inside the through hole 19.

[Example 2] FIG. 9 shows an example of another element structure according to the present invention.

In this embodiment, similarly to the previous embodiment, an insulating film 14, a conductive layer 15, and an insulating film 16 are laminated in a sandwich manner on the main surface of the semiconductor substrate 1. Further, a through hole 19 is formed so as to penetrate these layers, and this through hole 19 is filled with P-type single crystal silicon 21, which is not particularly limited, by laser annealing or epitaxial growth of polysilicon.

In this embodiment, impurities are diffused from the conductive layer 15 such as polysilicon sandwiched between the insulating films 4 and 16, so that the both sides of the through hole 19 are not reached to the center as shown in the figure. N+ type diffusion layers 3], a, and 31b are formed. However, in this case, the conductive layer 15 sandwiched between the insulating films 14 and 16 is divided into left and right parts to form separate extraction electrodes 15a and 15b, respectively, and a thin insulating layer is formed on the surface of the single crystal silicon 21. An electrode 33 is formed with a film (gate insulating film) 32 interposed therebetween.

As a result, an N-channel MOSFET (insulated gate field effect transistor) is formed in which the electrode 33 is used as a gate and the N+ type scattering layer 31a31b is used as a source and a drain, respectively.

Therefore, according to this embodiment, the area occupied by the MOSFET can be reduced and the degree of integration of the MO8 integrated circuit can be improved. Bipolar transistor and MOSF on the same substrate without sacrificing
ET can be easily formed.

Furthermore, a junction type FET (field effect transistor) is attached to the single crystal silicon 21 in the through hole 19 by the same method.
It is also possible to form

[Effect (1) On the main surface of the semiconductor substrate, an insulating film and a conductive layer are alternately stacked in a sandwich-like manner, and a hole passing through them is formed, and single crystal silicon is deposited in the hole in the parentheses. An active semiconductor is formed, and appropriate impurities are diffused into the semiconductor in the hole from the surface and the conductive layer between the substrate or an insulating film stacked on the substrate to form a diffusion layer that will become an active region. Since only the area that becomes the actual active area of the transistor element is formed in the single crystal silicon in the small-area hole, the area occupied by the transistor is reduced and high integration is possible. It has the effect of becoming.

(2) On the main surface of the semiconductor substrate, an insulating film and a conductive layer are alternately stacked in a sandwich-like manner, and a hole is formed through them, and a layer of monocrystalline silicon such as single crystal silicon is formed in the parenthesized hole. An active semiconductor is formed, and appropriate impurities are diffused into the semiconductor in the hole from this surface and the conductive layer between the substrate or an insulating film stacked on the substrate to form a diffusion layer that will become an active region. As a result, only the area that will become the effective active area of the transistor element is formed in the single crystal silicon in the small-area hole, which reduces the capacitance between the base and collector of the bipolar 1 and the transistor, and the collector and substrate. This has the effect of reducing the capacitance between the transistors and improving the performance of the transistor.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the through hole formed in the laminated structure of the insulating film and the conductive layer on the substrate is filled with single crystal silicon, but the semiconductor to be filled is not limited to silicon, but gallium - It may be a semiconductor such as arsenic.

Furthermore, in the above embodiment, apart from the NPNI-transistor formed in the single crystal silicon in the through hole, the N+ type scattering layer 12 and the P+ type diffusion layer 3 formed on the main surface of the substrate are used to form a horizontal type transistor. A P N P l-transistor may be configured.

[Field of Application] The present invention is applicable not only to bipolar integrated circuits and MO8 integrated circuits, but also to integrated circuits in which bipolar transistors and MOSFETs are mixed, and other bioconductor integrated circuits in general.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of the configuration of a bipolar transistor in a conventional semiconductor integrated circuit device, and FIGS. 2 to 8 show an example of applying the present invention to a bipolar integrated circuit in the order of manufacturing steps. FIG. 9 is a cross-sectional view showing an embodiment of the present invention applied to an MO8 integrated circuit. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 3...P+ type diffusion layer (channels 1 hetsupa), 12...N+ type diffused layer 14
...First layer insulating film (SiC2), 15...-first conductive layer, 15a... Collector extraction electrode,
16°°°° Second layer insulating film, 17... Second conductive layer, 17a... Base extraction electrode, 18...
Third layer insulating film, 19...through hole, 20...polysilicon, 21...r active semiconductor (single crystal silicon), 22...N+ diffusion layer, 23...・Third conductive layer (polysilicon), 23a... polysilicon electrode for emitter, 24... P+ type diffusion layer (base region) 25... N+ type scattered layer emitter region) , 28'
a, 28b...contact hole, 31a, 31b
...N+ type scattered layer source, drain region), 32
...Gate insulating film, 33...Gate electrode. Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. An insulating film and a conductive layer are alternately laminated on the main surface of a semiconductor substrate, and a hole is formed that penetrates the stiff insulating film and the conductive layer to reach the main surface of the substrate. A semiconductor device characterized in that the hole is filled with an active semiconductor, and a diffusion layer constituting a semiconductor element is formed in a part of the active semiconductor and is in contact with the conductive layer. 2. A diffusion layer of a conductivity type opposite to that of the substrate is formed on the main surface of the substrate directly below the active semiconductor in the hole, and a diffusion layer of the main surface of the substrate is formed below the active semiconductor in the hole. A diffusion layer of the same conductivity type as the bottom layer is formed to contact the first conductive layer, and a diffusion layer of the same conductivity type as the bottom diffusion layer is formed on top of the active semiconductor to form the third layer. Claim 1, characterized in that the first conductive layer is in contact with the second conductive layer, and further a diffusion layer of a different conductivity type is formed below the diffusion layer and connected to the second conductive layer. 1. Semiconductor device described in Section 1. 3. The semiconductor device according to claim 1 or 2, wherein the first and second conductive layers serve as extraction electrodes for corresponding diffusion regions, respectively. .