JPS6022336A - Master slice type semiconductor device - Google Patents

Abstract

PURPOSE:To devise effective use of the area of a semiconductor tip by giving logic function to the unused I/O cell of a master slice type semiconductor device and making it carry out logic circuit operation connecting to a basic cell region by wiring. CONSTITUTION:In the I/O cell region A of a master slice type semiconductor device, I/O cell 301, 302, 303... are provided. Among these I/O cells, cell 302 and cell 303 are used as an I/O cell but cell 301 is unused. On the other hand, in a core region B, a basic cell is provided and given logic function by wiring connection. If sufficient logic function cannot be carried out by the insufficient number of basic cells in the core region B, the unused I/O cell 301 is given logic function and is made as cell 201 which can carry out required logic function being connected to the basic cell by wiring. Since the unused I/O cell is utilized, the area of the tips is effectively used.

Description

[Detailed description of the invention] [Technical field to which the invention belongs] The present invention relates to a master slice type semiconductor device.

[Prior art and its problems] Conventionally, when developing a large-scale logic IC, the time required for the design and manufacturing process was enormous. As a means to overcome this problem, a master slice type semiconductor device has been proposed in which an LSI having a desired logical function can be developed by simply changing the wiring process for connecting elements.

An example is shown in FIG.

There is a region 101 (core region) in the center of the chip where basic cells that can provide various logical functions by wiring connections are arranged in a matrix, and a region 101 (core region) in the periphery thereof.
I1 is a circuit dedicated to interface with the outside of the chip.
It consists of an I76 cell area 102 in which 0 cells are arranged.

In the logic IC, all 10 cells of the I10 cell area are not used, and the I cells are used in accordance with the required number of pins, and the rest are empty areas.

As the number of gates (the number of basic cells) increases in such master slice type semiconductor devices, there are cases where the core area alone cannot perform the logical function.In such cases, the problem of increasing the chip area arises. However, there was a problem in that it also led to an increase in manufacturing costs and packaging costs.

[Objective of the invention] To effectively use chip area and overcome conventional problems by giving unused I/cells a logic function other than driving (logical function equivalent to that of the core area). aim at something.

[Summary of the Invention] When a master slice type semiconductor device becomes large-scale, a large number of input/output pins are required. Tsumashi I7. The Gai I10 cell region, which has a large number of cells, occupies a large area. In this case, 10 unused cells also exist, and the chip area becomes large. This unused part I7. In order to use cells effectively, the unused portion I7. This is because the cell has the same logical function as the core area.

[Effects of the Invention] Within the area of a co-master slice type semiconductor device, KI/cell free area other than the core area with logical functions can be made to have the same function as the core area, thereby making the % cell free area effective. If the logic function of the core area alone is not enough, it can be realized using the empty cell area, making effective use of the chip area. I7 of semiconductor device.
An enlarged view of the cell region (4) and an enlarged view of the core region (B) are shown. 201 is an unused I10 cell, and if left as is, it would become a wasted empty area, so in order to use this empty area effectively, it should be given the same logic function as the core area and connected by wiring, like 301. and use it.

By doing this, the unused I10 cells can be used effectively, and when the logic function of the core area alone is insufficient,
Unused I10 cells can be used.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a master slice type semiconductor device;
3 and 3 are plan views of the % cell area and core area of the master slice type semiconductor device. In fig. 202, 203, 302, 303...driving circuit used for interface with the outside, 201...unused cell, 301...using unused % cells to provide the same logic function as the core area part. I10 cell 0 that I made to have

Claims (1)

[Claims] Basic cell areas arranged in a matrix and their surroundings I1
In a master slice type semiconductor device having a 0 cell area, an unused I7o cell is given the same function as the basic cell, and the basic cell area and this I10 cell are connected with wiring to realize logic circuit operation. A master slice type semiconductor device characterized by: