JPS60224191A - Dynamic RAM - Google Patents

Abstract

PURPOSE:To attain high speed scroll with simple constitution by selecting a word line and reading storage information of a memory cell to a complementary data line to bring an adjacent word line into the selecting state, thereby transferring the information to a memory cell of the word line. CONSTITUTION:In bringing, for example, an odd number order of word line WL1 into the selecting state, an adjacent word line WL0 is brought into the selecting state with a delay to the line WL1 by an FET9 to which a word line selection timing signal phix1' is fed by the selection of the line WL1 by means of an address decoder DCR3. Thus, the storage content of all memory cells connected to the line WL1 read to the complementary data line with the selection of the line WL1 is transferred to all the memory cells connected to the line WL0 and written. The similar repetition is executed at each operating cycle to attain high speed scroll by the dynamic RAM forming the refresh memory with simple constitution.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a dynamic RAM (random access memory). It's about technology.

[Background technology]

When displaying a figure on a CRT (cathode ray tube), logic "0" and logic "1" information according to the dots that make up the figure are written in a storage device, and the information is written in synchronization with the CRT's rask scan timing. , is performed by reading out the above information. When dynamic RAM is used as such a refresh memory, when realizing the scroll function, it is necessary to read/write information bit by bit.
Since it is necessary to perform a write operation, scrolling takes a long time.

The inventor of the present application focused on the fact that in a dynamic RAM, one bit of information is stored in the form of an information storage capacitor with or without charge, and aimed at speeding up information transfer. I thought about it.

Note that the dynamic RAM is disclosed in Japanese Patent Application Laid-Open No. 57-8228.
It is described in detail in Publication No. 2.

[Purpose of the invention]

An object of the present invention is to provide a dynamic RAM with a simple configuration and new effective functions.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, after selecting a certain word line and reading out the information stored in the memory cell onto the data line, the adjacent word line is brought into a selected state to transfer information to the adjacent memory cell. .

〔Example〕

FIG. 1 shows a dynamic RA according to an embodiment of the present invention.
A circuit diagram of M is shown.

In the example circuit shown in the figure, O3FE between n channels
l G F E T (l n5ula
tedGate Field Effect Tran
This will be explained using the example ``sister''.

A 1-bit memory cell MC, as shown as a representative, has an information storage capacitor Cs and an address selection M
The information of logic "1", @0 is stored in the form of whether the capacitor Cs has charge or not.To read the information, MO3FETQm is turned on and the capacitor Cs is connected to the common data line. DL and senses how the potential of the data line DL changes depending on the amount of charge accumulated in the capacitor Cs.

The memory cells MC are formed small and the common data line D
Since many memory cells are connected to L to form a highly integrated and large capacity memory matrix, the capacitor Cs and
Regarding the relationship with the stray capacitance Co (not shown) of the common data line DL, the ratio Cs/CO becomes a very small value. Therefore, the change in the potential of the data line DL due to the amount of charge accumulated in the capacitor Cs is a very small signal.

A dummy cell DC is provided as a reference for detecting such a minute signal. This dummy cell DC is
Memory cell MC except that the capacitance value of capacitor Cd is half that of capacitor Cs of memory cell MC.
It is made under the same manufacturing conditions and with the same design constants. Capacitor Cd is connected to MO3FET prior to addressing.
The capacitor Cd is charged to the ground potential by Qd''. As mentioned above, since the capacitance value of the capacitor Cd is set to about half that of the capacitor Cs, the reference voltage equal to half of the read signal from the memory cell MC. will be formed.

In the figure, SA is a sense amplifier that expands the difference in potential change caused by the addressing into a sensing period determined by a timing signal (sense amplifier control signal) φpaLφpa2 (its operation will be described later),
Its input/output nodes are coupled to a pair of complementary data lines DL, DL arranged in parallel. Complementary data lines DL, D
The number of memory cells coupled to L is made equal to increase detection accuracy, and one dummy cell is coupled to each of DL and DL. Moreover, each memory cell MC is
One word line WL is coupled to one of the complementary pair data lines at the intersection. Since each word line WL crosses both data line pairs, even if a noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component will be transmitted to both data line pairs DL, DL. They appear equally and are canceled by the differential sense amplifier SA.

In the above addressing, complementary data line pair DL, D
When a memory cell MC coupled to one of the data lines L is selected, one of the pair of dummy word lines DWL, DWL is selected so that the dummy cell DC is always coupled to the other data line.

The sense amplifier SA has a pair of cross-wired MO3
FETQ1. Q2, and due to these positive feedback effects,
A minute signal appearing on complementary data lines DL, DL is differentially amplified. This positive feedback operation is performed in two stages, and the MO3FE has relatively low conductance characteristics.
It starts at the same time that TQ7 starts to conduct due to a relatively early timing signal φpal, and based on the potential difference given to the complementary data lines DL and DL by addressing, the higher data line potential is at a slow speed, and the lower one is at a faster speed. Together, the gap widens and declines. At this time, at the timing when the above-mentioned difference potential becomes large to a certain extent, the MO3FETQ8 is changed to a relatively large conductance characteristic.
is made conductive by the timing signal φpa2, so the potential of the lower data line drops rapidly. Like this 2
By operating the sense amplifier SA in stages, the drop in the higher potential is prevented.

In this way, when the lower potential drops below the threshold voltage of the cross-coupled MOS FET, the positive feedback operation ends, and the higher potential remains lower than the power supply voltage Vcc and higher than the threshold voltage. At the same time, the lower potential finally reaches the ground potential (Ov).

During the above-mentioned addressing, the stored information in the memory cell MC, which is about to be destroyed, is recovered by directly receiving the high-level or low-level potential obtained by this sensing operation. However, as described above, if the high level drops by more than a certain level with respect to the power supply voltage Vcc, a malfunction occurs that is read as a logic &01+ while reading and rewriting are repeated several times. An active restore circuit AR is provided to prevent this malfunction. This active restore circuit AR is activated by a timing signal φres (not shown), and has the function of selectively boosting only high-level signals to the potential of power supply voltage Vcc without having any effect on low-level signals.

A data line pair DL, which is shown as a representative in the figure,
DL is MO3FET that constitutes the column inch cw
Q3. Common complementary data line pair CDL, CD via Q4
Connected to L. Similar MO3FETQ5. It is connected to the common complementary data line pair CDL, CDL via QG. This common complementary data line pair CDL, CDL is connected to the remote terminal of the data output buffer DOB including the output amplifier and the output terminal of the data input cover sofa DIH.

The row decoder and column decoder R, C-DCR are 7
In response to an internal complementary address signal formed by the F L/ shuffer ADH, one word line, a dummy word line, and a column switch selection signal are formed to address memory cells and dummy cells. That is, the address buffer ADH forms an internal complementary address signal according to the applied external address signal AXO-AXi, and converts the internal complementary address signal to the row decoder in synchronization with the timing signal φar formed by the row address strobe signal RAS. Send to R-DCH. Row decoder R
-DCR receives this internal complementary address signal and word line selection timing signal φX and performs a selection operation of a predetermined word line and dummy word line. In this embodiment, in order to perform scrolling and the like as described later at high speed, in addition to the word line selection timing signal .phi.X, a word line selection timing signal .phi.X' which is generated later than the word line selection timing signal .phi.X is also supplied.

Further, the address buffer ADB forms an internal complementary address signal according to the applied external address signal AYO=AYi, and transfers it to the column in synchronization with the evening/f timing signal φac formed by the column address strobe signal CAS. Send to decoder C-DCR. Column decoder CDCR receives this internal complementary address signal and data line selection timing signal φy to perform a data line selection operation.

The timing generation circuit TG receives a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE from external terminals, although not particularly limited thereto, and forms various timing signals necessary for the above operations.

FIG. 2 shows a circuit diagram of an embodiment of the row decoder R-DCH.

In the row decoder circuit of this embodiment, the address decoder section is divided into two in order to minimize the interval (pitch) between word lines. That is, the second address decoder unit DCR2
is the representatively shown NOR gate circuit NOH
An address decoder output signal that simultaneously selects four word lines WLI to WL4 is formed as shown in FIG. This address decoder output signal is transmitted to the cut MO3FETQI1 to Q1 to which the power supply voltage Vcc is constantly applied to the gate.
4 to the gates of transmission gates MO3FETQI 5 to Q18. On the other hand, according to the remaining 2 bits of address signals for word line selection, the first address decoder unit DCR1 forms four word line selection timing signals φx00 to φxll, which are output to the transmission gate MO3.
Word line WL through FETQI 5 to Q18 respectively.
It is communicated to I~WL4. By doing so, the pitch of the NOR gate circuits NOR etc. constituting the first address decoder section can be matched with the pitch of the word lines.

Further, in order to speed up operation functions such as scrolling, the word line WLO is provided with an MO3FET QI 9 that receives a selection signal from the adjacent word line WL1. Further, word line WLI is provided with a MOS FETQ20 that receives a selection signal from adjacent word line WL2. In this way, each adjacent word line Wn is provided with a MOSFET that receives the selection signal of the adjacent word line Wn+1. Among the MO3FETs QI9 to Q22 shown as representatives above, odd numbered word lines WL1. MO3FETQ20 installed in WL3 etc.
Q22 and the like are connected to the word line selection timing signal line φXO°, and MO3FET QI9°Q21 and the like provided on even numbered word lines WLO, WL2, etc. are connected to the word line selection timing signal φx1°. These word line selection timing signals φXO゛ φx1゛ are formed by the third address decoder section DCR3. That is, when the address decoder unit DCR3 receives internal complementary address signals aO and aO and selects an odd numbered word line, it forms a word line selection timing signal φx1 according to the word line selection timing signal φX°, and selects an even numbered word line. When the word line numbered is selected, the word line selection timing signal φxO according to the word line selection timing signal φX
form.

Note that the word line selection timing signal φX'' is not particularly limited, but as described later, when the column address strobe signal CAS is set to a low level before the row address strobe signal RAS is set to a low level, the word line selection timing signal φX'' is generated by the timing generation circuit TO. , which is generated at a predetermined timing.

Next, the operational functions of the dynamic RAM newly provided by the above embodiment circuit according to the timing diagram shown in FIG. 3 will be explained.

In this embodiment, although not particularly limited, the column address strobe signal CAS is set to the low level before the row address strobe signal RAS is set to the low level. In this state, row address signals AXO to AXi
is taken into the address buffer ADB, and the address strobe signal RAS becomes low level later than the row address signal. Here, the reason why the RAS signal is delayed from the row address signals AXO to AXi is to ensure that the row address signals AXO to AXi are taken into the address buffer ADB.

Next, the signal φa formed by the low level of the RAS signal
r (not shown) is supplied to an address buffer, and internal complementary address signals axO to axi (see FIG. 1) corresponding to the latched row address signal are sent to a row address decoder R-DCR. Here, the internal address signal axO having the same phase as the external address signal AXO and the internal address signal -0 having the opposite phase are collectively expressed as an internal complementary address signal 0. The same applies to other complementary internal address signals. The row address decoder R-DCR is
The outputs of those selected according to the complementary address signals uO to axt are kept at high level, and those that are not selected are set to low level.

Then, the selected row address decoder R-DC
The output of R is sent to the memory array in synchronization with the word line selection timing signal φX delayed from the timing signal φar. In this way, one word line of the memory array and the corresponding dummy word line are selected, and the minute storage signal of the selected memory cell and the reference voltage of the dummy cell are read out to the complementary data line D.

Next, the timing signal φpa (φpal+φpa2
), the sense amplifier SA is activated and the amplification operation of the minute storage signal is performed.

Then, the active restore circuit AR is activated by the timing signal φres, and the high level of the complementary data line D is restored.

Thereafter, in this embodiment, the timing generation circuit TG identifies that the column address strobe signal CAS has changed to the low level first, and generates the word line selection timing signal φX°.

For example, when an odd-numbered word line WLI is brought into the selected state, the word line selection timing signal φχ1'' is generated by the address decoder section D CR,3, so that MO3, which is turned on by the selection of the word line WLI, is
Word line WLO is also brought into the selected state with a delay by FETQI 9. As a result, since the memory information of the memory cell connected to the word line WLI has already been read out to the complementary data line D, the selected memory cell is transferred to the complementary data line D by the selection operation of the word line WLO. Linear.

The information read out to D is written as is. That is, through the series of operations described above, all the stored information of the memory cells connected to the word line WLI is transferred to the memory cells connected to the word line WLO. The above operation completes one cycle of operation.

Next, when word line WL2 is selected and word line WLI is brought into the selected state with a delay in the same manner as above, all the stored information in the memory cells connected to word line WL2 is transferred to the memory cells connected to word line WLI. are transferred respectively. Hereinafter, by sequentially performing similar operations for all word lines,
In the figure, scrolling can be performed by transferring 1 degree bit of data from right to left.

Further, if the word line selection order is reversed from the above case, the clearing operation can be performed at high speed. That is, in the embodiment circuit shown in FIG. 2, the word line WL
This is because after selecting word line WL2 and transferring information to word line WL2, when word line WL2 is selected next, it is transferred to word line WLI. By writing logic "0" or logic "1" to all memory cells connected to the rightmost word line in the figure, all memory cells are set to logic @θ" or logic "1". Can be cleared.

Note that in normal write/read operations, the column address strobe signal CAS never becomes low level prior to the row address strobe signal RAS, so the word line selection timing signal φX' is never formed. Therefore, two word lines are never selected simultaneously during the same operating cycle.

〔effect〕

(l) By adding a function that selects one word line and reads out the stored information of the memory cell onto a complementary data line, the adjacent word line is selected. Since information stored in a memory cell can be simultaneously transferred to memory cells on adjacent word lines, operations such as scrolling can be performed at extremely high speed. By the way, the dynamic type R has a storage capacity of 64 bits.
In AM, the entire stored information can be moved by one bit in 255 cycles.

(2) By selecting the word lines in the opposite direction to the scrolling operation, it is possible to achieve the effect that the clearing operation can be performed at high speed.

(3) The above (l) is achieved by using an extremely simple circuit configuration in which an MO3F'ET receiving an adjacent word line selection signal is provided as the selection circuit for the adjacent word line.

The effect of (2) is that a dynamic RAM having new and effective functions can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment circuit shown in FIG. 2, by adding a MOS FET and a selection timing signal that selects the word line WLI when the word line WLO is in the selected state, selective scrolling can be performed in both the left and right directions. It is something that can be done.

Furthermore, any circuit may be used to select adjacent word lines as described above. Furthermore, a control signal for selectively performing such a double word line selection operation can be generated by adding a special external signal or by a combination of a row address strobe signal, a write enable signal, etc. Many embodiments can be adopted.

[Application field]

The present invention can be widely used in dynamic RAMs that store information in the form of charges.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the row decoder circuit, and FIG. 3 is a diagram showing the operation of the dynamic RAM according to the present invention. FIG. 3 is a Thai wording diagram for explaining an example. MC: memory cell, DC: dummy cell, CW: column switch, SA: sense amplifier, AR: active restore circuit, RC-DCR: row/column decoder, ADB: address buffer, DOB: data Output buffer, D! B...Data manual buffer, TG...
・Timing generation circuit 7A and θ~A4 in Fig. 1 Fig. 2 Fig. 3

Claims (1)

[Claims] 1. Information storage capacitor and address selection MO3FET
The memory array includes a memory array in which a plurality of memory cells are arranged in a matrix, and one word line of the memory array is selected and stored information read out to the data line is transferred to the selected word line. A dynamic RAM characterized by having a function of transferring data to an adjacent memory cell by setting an adjacent word line to a selected state. 2. The adjacent word line selection circuit is configured with a MOSFET that receives the word line selection signal and transmits a word line selection timing signal that is generated later than the word line selection timing signal. Dynamic type R according to claim 1, characterized in that
AM Yu 3, the transfer operation to the adjacent memory cell is selectively performed by a combination of control signals supplied from external terminals, as set forth in claim 1 or 2. Dynamic RAM.