JPS60224242A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60224242A JPS60224242A JP59079505A JP7950584A JPS60224242A JP S60224242 A JPS60224242 A JP S60224242A JP 59079505 A JP59079505 A JP 59079505A JP 7950584 A JP7950584 A JP 7950584A JP S60224242 A JPS60224242 A JP S60224242A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- parallel
- silicon
- film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明はシリコン選択エピタキシャル法を利用した半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor device using a silicon selective epitaxial method.
〈従来技術の問題点〉
近年、半導体デバイスにおける能動素子間の分離方法は
選択酸化法にかわる微細な素子分離技術が要求されてい
る。微細で深い素子分離領域を形成する方法としてたと
えば、電子通信学会技術研究報告５８Ｄ８３−５２の３
９ページから４５ページに「選択エピタキシャル成長に
よる素子分離」と題して発表された論文においては、シ
リコン（１００）面方位基板上１に第１図（ａ）、 （
ｂ）に示すようあらかじめ素子分離領域となるシリコン
酸化膜パターン２を（１１０）面方位と平行となるよう
に形成し、次いでその絶縁膜上には堆積することなく露
出したシリコン基板領域のみシリコンをエピタキシャル
成長させて第２図（、）、 （ｂ）に示すような基板が
形成されることが示されている。第２図に示した基板を
用いてＭＯＳ）ランジスタを形成するためにはエピタキ
シャル成長層３のＳ＋０２パターン２に接してファセッ
ト４が形成され、ゲート電極形成の際の障害となる。前
記ファセットをなくすために第３図のようＶｃｓｉｏｔ
側壁に多結晶シリコン膜６を形成し、次いでエピタキシ
ャル成長させると第４図に示すように平坦な基板が形成
される。第４図に示した基板を用いてＭＯＳ）ランジス
タを形成すると５ｉＯ１２との界面でのシリコン領域で
の単結晶化が十分に女されずｐ−ｎ接合でのリーク電流
の発生や絶縁耐圧の低下にともなう製造歩留シを低下さ
せる欠点があった。<Problems with Prior Art> In recent years, as a method for isolating active elements in semiconductor devices, a fine element isolation technique is required to replace the selective oxidation method. For example, as a method for forming a fine and deep element isolation region, see IEICE technical research report 58D83-52-3.
In the paper published on pages 9 to 45 entitled ``Element isolation by selective epitaxial growth'', a silicon (100)-oriented substrate 1 is coated with a silicon substrate (see Fig. 1(a)).
As shown in b), a silicon oxide film pattern 2 that will become an element isolation region is formed in advance parallel to the (110) plane orientation, and then silicon is deposited only on the exposed silicon substrate region without being deposited on the insulating film. It is shown that a substrate as shown in FIGS. 2(a) and 2(b) can be formed by epitaxial growth. In order to form a MOS transistor using the substrate shown in FIG. 2, a facet 4 is formed in contact with the S+02 pattern 2 of the epitaxial growth layer 3, which becomes an obstacle when forming a gate electrode. In order to eliminate the facet, Vcsiot as shown in FIG.
A polycrystalline silicon film 6 is formed on the side walls and then epitaxially grown to form a flat substrate as shown in FIG. When a MOS transistor is formed using the substrate shown in Fig. 4, the single crystallization in the silicon region at the interface with 5iO12 is not sufficiently suppressed, causing leakage current at the p-n junction and a decrease in dielectric strength. This has the disadvantage of lowering the production yield.
〈発明の目的〉
本発明は、上記のような従来の欠点を除去せしめて、絶
縁膜側壁に多結晶シリコン膜を形成することなく平坦な
部分を有する基板を形成する方法を提供することにある
。<Object of the Invention> An object of the present invention is to provide a method for eliminating the above-mentioned conventional drawbacks and forming a substrate having a flat portion without forming a polycrystalline silicon film on the side wall of an insulating film. .
〈発明の構成〉
本発明によれば（１００）面方位のシリコン単結晶層を
備えた基板上に絶縁膜を形成し、次いで該絶縁膜の所望
の部分に開口部を設け、次いで前記開口部にのみ選択的
に単結晶シリコン膜をエピタキシャル成長させ、前記開
口部にのみ選択的に単結晶シリコンを成長させ、エピタ
キシャル成長層に半導体デバイスを形成する半導体装置
の製造方法において、絶縁膜開口部の辺を（１００）面
と平行にし、前記絶縁膜とエピタキシャル成長層が平坦
となる部分にゲート電極を形成することを特徴とする半
導体装置の製造方法を与えるものである。<Structure of the Invention> According to the present invention, an insulating film is formed on a substrate including a silicon single crystal layer with a (100) plane orientation, an opening is provided in a desired portion of the insulating film, and then the opening is In a method for manufacturing a semiconductor device in which a single crystal silicon film is epitaxially grown selectively only in the opening, single crystal silicon is selectively grown only in the opening, and a semiconductor device is formed in the epitaxially grown layer. This invention provides a method for manufacturing a semiconductor device, characterized in that a gate electrode is formed in a portion parallel to the (100) plane and where the insulating film and the epitaxial growth layer are flat.
（構成の詳細な説明）
本発明は上述の構成をとることにより従来技術の問題点
を解決した。絶縁膜パターンの辺を（１００）面に平行
にすることによシ、多結晶シリコン膜がなくともエピタ
キシャル成長層と絶縁膜パターンが平坦になる部分が存
在する。その平坦な部分にゲート電極を形成すれば、微
細なゲート電極形成が可能である。また多結晶シリコン
膜が存在しないためエピタキシャル成長層は単結晶シリ
コンとなった。したがってｐ−ｎ接合でのリーク電流は
減少した。(Detailed Description of Configuration) The present invention solves the problems of the prior art by adopting the above-described configuration. By making the sides of the insulating film pattern parallel to the (100) plane, there is a portion where the epitaxial growth layer and the insulating film pattern are flat even without the polycrystalline silicon film. By forming a gate electrode on the flat portion, it is possible to form a fine gate electrode. Furthermore, since there is no polycrystalline silicon film, the epitaxially grown layer is made of single crystal silicon. Therefore, the leakage current at the pn junction was reduced.
（実施例）
以下本発明の実施例について図面を参照して詳細に説明
する。第５図（ａ）ｔ （ｂ）は本発明の実施例を示す
図である。面方位（１００）のｐ型単結晶シリコン基板
（比抵抗１５Ω・１）に熱酸化膜をウェット酸化によシ
２μｍの厚さに形成した後、通常の写真蝕刻技術と反応
性イオンエツチング法によって垂直断面をもつ８ ｉ０
２絶縁膜パターンを（１００）面に平行になるよう形成
し、次いで８ｉＨ１Ｃ１１とＨ！とから構成されるガス
系に約ＩＶｏ１％のＨＣＩを加え、９００℃から１１０
０℃の温度範囲で選択的にシリコン基板表面にのみシリ
コンを厚さ２μｍエピタキシャル成長させる。この場合
、ファセット１４が（１１１）面に平行に形成されるが
、（１００）面と平行な８ｉ０４との界面の中央部に平
坦な部分が存在する。(Example) Examples of the present invention will be described in detail below with reference to the drawings. FIGS. 5(a) and 5(b) are diagrams showing an embodiment of the present invention. After forming a thermal oxide film to a thickness of 2 μm by wet oxidation on a p-type single-crystal silicon substrate (specific resistance 15Ω·1) with plane orientation (100), it was etched by ordinary photolithography and reactive ion etching. 8 i0 with vertical section
2 insulating film patterns were formed parallel to the (100) plane, and then 8iH1C11 and H! Approximately IVo1% HCI was added to the gas system consisting of
Silicon is selectively epitaxially grown to a thickness of 2 μm only on the surface of the silicon substrate in a temperature range of 0° C. In this case, the facet 14 is formed parallel to the (111) plane, but a flat portion exists at the center of the interface with 8i04 parallel to the (100) plane.
次いで９５０℃の０．中で厚さ２００Ｘのゲート酸化膜
１５を形成し、イオン注入によシホウ素を加速エネルギ
ー３０ ＫｅＶでＩ Ｘ １０”″（Ｉｌｌ−”と加速
エネルギー１００ ＫｅＶで２ Ｘ １０” ＠−”の
二重注入をする。次いで減圧ＣＶＤ法によりポリシリコ
ン膜を厚さ５０００ Ｘ堆積した後、写真蝕刻法とドラ
イエツチング法によシ平坦な部分にゲート電極を形成し
、次いでセルフ−アラインでヒ素を加速エネルギー１０
０ ＫｅＶで５ Ｘ １０′ｌｌｍ−”イオン注入し、
前記ポリシリコンゲート電極に拡散法によりリンをドー
プすると第６図（、）の断面構造が得られる。次いで減
圧ＣＶＤ法によｐ ８ｉ０１膜１８を厚さ５０００ Ｘ
堆積しコンタクトホールを形成する。次いで電子ビーム
蒸着法によシ厚さ１μｍのＡＩ膜を堆積し、通常のリン
グラフィ法によりてＡ１配線１９を形成する。次いでパ
ッシベーＶｉ１ン膜を形成し、コンタクトをあけると第
６図（ｂ）に示すような断面構造を有するｎチャネルＭ
Ｏ８ＦＥＴが得られる。Then 950°C 0. A gate oxide film 15 with a thickness of 200X is formed in the inside, and ions of boron are implanted into two layers: I. Then, after depositing a polysilicon film to a thickness of 5000× by low pressure CVD, a gate electrode is formed on the flat part by photolithography and dry etching, and then arsenic is accelerated by self-alignment. energy 10
5 x 10'llm-'' ion implantation at 0 KeV,
When the polysilicon gate electrode is doped with phosphorus by a diffusion method, the cross-sectional structure shown in FIG. 6(,) is obtained. Next, the p8i01 film 18 was formed to a thickness of 5000× by low pressure CVD method.
Deposit to form contact holes. Next, an AI film with a thickness of 1 μm is deposited by electron beam evaporation, and an A1 wiring 19 is formed by ordinary phosphorography. Next, a passivation film is formed, and when a contact is made, an n-channel M having a cross-sectional structure as shown in FIG. 6(b) is formed.
An O8FET is obtained.
（発明の効果）
本発明と従来の方法から製造されたダイオードの逆バイ
アスにおける電流特性を第７図に示す。(Effects of the Invention) FIG. 7 shows the current characteristics in reverse bias of diodes manufactured by the present invention and the conventional method.
本発明によれば一般にＭＩ８ＦＥＴの製造プロセスが簡
略化でき、接合リーク電流の減少に対し有効である。According to the present invention, the manufacturing process of MI8FET can generally be simplified and is effective in reducing junction leakage current.
第１図（、）と（ｂ）はそれぞれ素子分離領域の形状を
示す正面図と断面図である。
第２図は、第１図の構造に対し選択エピタキシャル成長
した後の形状を示す正面図（、）と断面図（ｂ）である
。
第３図は８ｉ０１側壁にポリシリコン薄膜を形成した基
板の断面図である。
第４図は第２図の構造を有する基板にシリコンを選択エ
ピタキシャル成長した後の断面図である。
第５図は本発明の実施例における基板の構造を示方法を
示す断面図である。
第７図は従来方法と本発明で得られたダイオードの逆バ
イアス電圧と接合電流の関係を示しだ図である。
図において
１．１１・・・（ｉｏｏ） ｓ ＋単結晶基板、２，１
２・・・絶縁膜パターン、３．１３・・・エピタキシャ
ルシリコン層、４．１４・・・ファセット、５・・・多
結晶シリコン薄膜、１５・・・ゲート酸化膜、１６・・
・ゲート電極、１７・・・高濃度イオン注入されたｎ十
層、１８、２０・・・ＣＶ Ｄ ８ｉ０ｘ膜、１９・・
・配線アルミニウム膜、ａ・・・本発明による電圧電流
特性、
ｂ・・・従来方法による電圧−電流特性。
第１図
（Ｑ）
第２図
第３図
２
第５図
１
第６図
第７図
５ １０ １５
這バ゛イアス＠ｆｆｉ （ν）FIGS. 1(a) and 1(b) are a front view and a cross-sectional view, respectively, showing the shape of the element isolation region. FIG. 2 is a front view (,) and a cross-sectional view (b) showing the shape of the structure shown in FIG. 1 after selective epitaxial growth. FIG. 3 is a cross-sectional view of a substrate with a polysilicon thin film formed on the 8i01 sidewall. FIG. 4 is a sectional view after silicon has been selectively epitaxially grown on the substrate having the structure shown in FIG. FIG. 5 is a sectional view showing a method of showing the structure of a substrate in an embodiment of the present invention. FIG. 7 is a diagram showing the relationship between reverse bias voltage and junction current of diodes obtained by the conventional method and the present invention. In the figure, 1.11...(ioo) s + single crystal substrate, 2,1
2... Insulating film pattern, 3.13... Epitaxial silicon layer, 4.14... Facet, 5... Polycrystalline silicon thin film, 15... Gate oxide film, 16...
・Gate electrode, 17... High concentration ion implanted n10 layer, 18, 20... CV D 8i0x film, 19...
- Wiring aluminum film, a... Voltage-current characteristics according to the present invention, b... Voltage-current characteristics according to the conventional method. Figure 1 (Q) Figure 2 Figure 3 2 Figure 5 1 Figure 6 Figure 7 5 10 15 Bias @ffi (ν)
Claims (1)
絶縁膜を形成し、次いで該絶縁膜の所望の部分に開口部
を設け、次いで前記開口部にのみ選択的に単結晶シリコ
ン膜をエピタキシャル成長させ、エピタキシャル成長層
に半導体デバイスを形成する半導体装置の製造方法にお
いて、絶縁膜開口部の辺を（１００）面と平行にし、前
記絶縁膜とエピタキシャル成長層が平坦となる部分にゲ
ート電極を形成することを特徴とする半導体装置の製造
方法。An insulating film is formed on a substrate having a silicon single crystal layer with (100) plane orientation, an opening is formed in a desired portion of the insulating film, and a single crystal silicon film is selectively formed only in the opening. In a method for manufacturing a semiconductor device in which a semiconductor device is formed in an epitaxially grown layer by epitaxial growth, the sides of an opening in an insulating film are made parallel to a (100) plane, and a gate electrode is formed in a portion where the insulating film and the epitaxially grown layer are flat. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59079505A JPH077793B2 (en) | 1984-04-20 | 1984-04-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59079505A JPH077793B2 (en) | 1984-04-20 | 1984-04-20 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60224242A true JPS60224242A (en) | 1985-11-08 |
| JPH077793B2 JPH077793B2 (en) | 1995-01-30 |
Family
ID=13691794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59079505A Expired - Lifetime JPH077793B2 (en) | 1984-04-20 | 1984-04-20 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH077793B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344725A (en) * | 1986-04-02 | 1988-02-25 | Toshiba Corp | Manufacture of semiconductor device |
| US5447883A (en) * | 1993-10-29 | 1995-09-05 | Nec Corporation | Method of manufacturing semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5227037A (en) * | 1975-08-26 | 1977-03-01 | Commissariat Energie Atomique | Vacuum separating valve for electron bombardment welding machine |
| JPS544230A (en) * | 1977-06-13 | 1979-01-12 | Kubota Ltd | Age hardening, wear resistant ni alloy |
| JPS5928330A (en) * | 1982-08-10 | 1984-02-15 | Nec Corp | Vapor growth method of semiconductor |
-
1984
- 1984-04-20 JP JP59079505A patent/JPH077793B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5227037A (en) * | 1975-08-26 | 1977-03-01 | Commissariat Energie Atomique | Vacuum separating valve for electron bombardment welding machine |
| JPS544230A (en) * | 1977-06-13 | 1979-01-12 | Kubota Ltd | Age hardening, wear resistant ni alloy |
| JPS5928330A (en) * | 1982-08-10 | 1984-02-15 | Nec Corp | Vapor growth method of semiconductor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344725A (en) * | 1986-04-02 | 1988-02-25 | Toshiba Corp | Manufacture of semiconductor device |
| US5447883A (en) * | 1993-10-29 | 1995-09-05 | Nec Corporation | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH077793B2 (en) | 1995-01-30 |
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