JPS60224320A - And circuit - Google Patents

Abstract

PURPOSE:To prevent the output of a rectifying circuit from being affected by the spike noise which is generated when the output level of an AND operating oscillator is changed, by providing a clamping circuit in the input side of the rectifying circuit. CONSTITUTION:The oscillation output of an AND operating oscillator 1 is supplied to a clamping circuit 2 provided with the first circuit 20 and the second circuit 21. The clamping circuit 2 clamps the input signal to a rectifying circuit 3 in a potential having a characteristic opposite to that of the potential of a terminal for power supply connected to the rectifying circuit 3. That is, the first circuit 20 in the clamping circuit 2 clamps the oscillation output from the oscillator 1 in an earth potential and supplies it to the rectifying circuit 3. Thus, the oscillation output of the oscillator 1 is rectified and outputted from the rectifying circuit 3. As the result, the output of the rectifying circuit is not affected by the spike noise due to the change of the output level of the AND operating oscillator.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention has an AND operation oscillator with multiple inputs, and a rectifier circuit that rectifies its output, such as an AND circuit used in a railway signal processing device. Concerning AND circuits.

Conventional technology The output signal of a multiple-input AND operation oscillator is processed by a rectifier circuit.
Various AND circuits have been proposed that double the voltage and use the rectified output as the circuit output (Japanese Patent Publication No. 45-2905
No. 4, Utility Model Publication No. 57-4764). However, in conventional AND circuits of this kind, the AND operation oscillator is configured to oscillate only when each input signal is at a predetermined level, so when all input signals are not at a predetermined level, The DC output of the AND operation oscillator is at L level (
However, when one of the input signals reaches a predetermined level, the DC output of the AND operation oscillator changes from L level to H level (or vice versa), or vice versa. When the input signal that had reached the level no longer reaches the predetermined level, the DC output of the AND operation oscillator changes from the H level to the low level (or from the low level to the high level). Due to the change, the DC output level of the AND operation oscillator may change, and this change has the disadvantage that a spike N sound is generated in the output of the rectifier circuit.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an AND circuit that is not affected by spike noise when the output level of an AND operation oscillator changes.

Structure of the Invention In order to achieve the above object, the present invention provides a clamp circuit that clamps an input signal to a rectifier circuit to a potential of opposite polarity to the potential of a power supply terminal connected to the rectifier circuit, on the signal input side of the rectifier circuit. It is characterized by the fact that it is provided in

Example The present invention will be described below based on embodiments shown in the drawings.

FIG. 1 shows an example of an AND circuit operated by two people. In the figure, (1) is an AND operation oscillator that has upper and lower thresholds and does not oscillate due to a failure of a circuit element, and (2) is an AND operation oscillator that has upper and lower thresholds and does not oscillate due to a failure of a circuit element. A clamp circuit that clamps the output signal of the product operation oscillator (1) to a predetermined potential, (3) is the clamp circuit (2)
This is a rectifier circuit that rectifies and smoothes the output signal. This AND circuit connects the AND operation oscillator (1) to a terminal (T1.T
2>, apply the voltage (E) of the power supply for the AND operation oscillator (1) between the terminals (T3 and T4), set the terminal (T3) as the positive terminal, and ) is the negative terminal, and the output terminals (T5, T6) of the rectifier circuit (3)
The signal obtained during this period is defined as the circuit output of the AND circuit.

In the example of FIG. 1, the AND operation oscillator (1) is an oscillator that operates as a window comparator as a whole, but it has individual sensitivity to the input signal to the terminal (TLT2), and Two circuits (10, 11) that individually follow (T1.Eng.2) and determine sensitivity, and a phase inversion circuit that is provided so that both circuits (・10.11) can perform dependent oscillation. (12), but it may also be a well-known AND operation oscillator. In addition, the circuit (1
0, 11) are transistor delay circuits, but in the following description, for convenience, the circuits (10, 11) will be referred to as window comparators.

Each window comparator (10, 11) is composed of three transistors (Ql, Q2) connected in series in the illustrated example.
．． Q3 ) (Q5.Q6.Ql ) and eight resistors (R
1, R2, R3, R4, R5, R6, R7, R8) (
R4l.

R12, R13, R14, R15, R16, R17, R
18). Transistor (Q2) and (
Q3), (Q6), and (Ql) are complementary transistors. Also, transistors (Q2) and (Q
6) plays the role of an amplifier whose power source is E.

Transistor (Ql) of window comparator (10)
), the output of the transistor (Ql) of the window comparator (11) is connected to the collector resistor (R16, R1
7) and input via the resistor (R18),
A transistor (Ql) is connected to the base of the transistor (Q2).
) is input by dividing the voltage including the level shift of the power input to the terminal (T3) by the resistors (R2, R3), and the base of the transistor (Q3) is connected to the transistor (Q2).
The output of the transistor (Q3) is inputted after being divided by the resistors (R4, R5), and the output of the transistor (Q3) is input to the collector resistor (R
6, R7) and is supplied to the phase inversion circuit (12) via a resistor (R8). This window comparator (10) connects the power input to the terminal (T3) to E and the terminal (
11, the input to T1), and the resistors (R1, R2, R3, R6
, R7) are respectively R1, R2, R3, R6, R7
Then, (R4→-R2+R3)E (R6+R7)E, <
It oscillates under the condition l1<□R3R5 (hereinafter referred to as equation 1).

Transistor (Q5) of window comparator (11)
) is inputted with the output of the phase inversion circuit (12),
The base of the transistor (Q6) is connected to the transistor (Q5).
) output is connected to terminal (I3) by resistor (R12, R13)
The voltage is divided and input including the level shift of the power input to the transistor (Ql), and the base of the transistor (Ql) is
The output of 6) is voltage-divided by resistors (R14, R15) and input.

This window comparator (11) is connected to the terminal (I3)
The input signal to the E1 terminal (I2) is 12,
If the resistance values of the resistors (R11, R12, R13, R16, R17) are R11, R12, R13, R16, R17, respectively, (R11+R12+R13)E (R16+R17)E
, <12<□ R13R17 (hereinafter referred to as equation 2). The output of this window comparator (11) can be, for example, the collector output of the transistor (Q6).

The phase inversion circuit (12) consists of a transistor (Q4) and two
11ii1 resistors (R9, R10).

The base of the transistor (Q4) is connected to the output terminal of the window comparator (10), and the collector is connected to the terminal (
T1) via a collector resistor (R9), and is also connected via a resistor (R10) to the base of the transistor (Q5) of the window comparator (11), and its emitter is connected to the terminal (I3). .

In this AND operation oscillator (1), when the input signal (11) to the terminal (T1) exceeds the upper limit threshold, the transistor (Q4) remains on, and the input signal (11) to the terminal (T1) exceeds the lower limit threshold. If not, the transistor (Q2) remains on. Also, if the input signal (I2) to the terminal (T?) exceeds the upper threshold, the transistor (Ql) remains on, and if it does not reach the lower threshold, the transistor (Q6) remains on. ) or remain on.

However, when the input signal (I2) to the terminal (I2) satisfies the oscillation conditions of the above two formulas, and the input signal (11) to the terminal (T1) satisfies the oscillation conditions of the first formula, The AND operation oscillator (1) oscillates as each transistor operates as follows.

That is, Q2 off → Q3 off → Q 4 on → Q5 off →
Q6 off → Q7 off → Q on → Q2 on → Q3
・On→Q 4・Off→Q5・On→Q6・On→・・
...and oscillates. [If the input signal (I1) to the terminal (T1) satisfies the oscillation conditions of formula 1 above, the input signal (12) to the terminal (I2) satisfies the oscillation conditions of formula 2 above. Then, in the AND operation oscillator (1), each transistor is Q6 off → Q7 off → Q on → Q2 on → Q
3.On → Q4.Off → Q5.On → Q6.On → Q7
・Oscillates by turning on → Q off → Q2 off.

Even if any of the circuit elements (R1-R17) and (01 to Q7) constituting the AND operation oscillator (1) has a short circuit or disconnection failure, the AND operation oscillator (1) does not oscillate.

The output of fヱ, -1T, -'s vagina track tracking device 11) oscillates only when the input signals to the terminals (TI, I2) both satisfy the oscillation conditions, so that the output can be connected to the ground at a specified distance. The signal shown in FIG. 2(a) changes between levels (e). However, for example, when no input voltage is applied to the terminal (T1) that satisfies the oscillation conditions of the first equation (therefore,
The AND operation oscillator (1) does not oscillate) and the terminal (I2
), when a signal that satisfies the above two equations is input to the transistor (
Q6) turns off, so the power supply potential (E) changes to the ground level, and conversely, when the input signal to terminal (I2) disappears while the transistor (Q6) is off, the transistor (Q6) turns on. , changes from the ground level to the power supply potential (E). This results in a noise whose DC level changes as shown in Figure 3 (a).

“The clamp circuit (2) includes a first circuit (20) that clamps the output of the AND operation oscillator (1) to the zero potential, or ground potential, at the terminal (I4), and a first circuit (20) that clamps the output of the AND operation oscillator (1) to the zero potential, that is, ground potential, at the terminal (I3). The first circuit (20) includes a coupling capacitor (22) into which the output of the AND operation oscillator (1) is input, and a coupling capacitor (22) whose emitter is connected to the output of the capacitor (22). an NPN transistor (24) connected to the side and whose base is connected to the terminal (T4) via a resistor (23), and a diode (25) connected between the base and emitter of the transistor (24) to clamp it negatively. ).The second circuit (21) includes a coupling capacitor (26) to which the output of the AND operation oscillator (1) is input, a resistor (27) provided on the output side of the coupling capacitor (26), and a capacitor. (26) and the resistor (27) is connected to the terminal (T3) to positively clamp the diode (28).

The collector of the transistor (24) and the output side of the resistor (27) are connected to a wired OR, and are connected to the signal input terminal of the rectifier circuit (3) at the next stage.

Here, the transistor (24) is connected to the clamp circuit (2)
When there is no input signal, there is no conduction between the collector and emitter as described later, so when there is no input signal, the resistors (R23) and (R2
7), that is, R27<<R23, so approximately the power supply potential (E) is applied to the rectifier circuit (3) of the next stage.
It is inserted to give to

The rectifier circuit (3) has a fail-safe structure in which the output is provided only when the oscillation output of the AND operation oscillator (1) is input, and there is no output when the oscillation output is not input or there is a circuit failure. This is an n-fold voltage rectifying and smoothing circuit created, and is connected so that the terminal (T3) side outputs zero potential. For example, in the case of a voltage doubler rectifier circuit, such a rectifier circuit (3) has a coupling capacitor (30) and two diodes provided on its output side, as shown in the figure.
31, 32> and a four-terminal capacitor (33).

Next, the clamp circuit (2) in the above-mentioned AND circuit
The operation of the rectifier circuit (3) will be explained.

First, because the AND operation oscillator (1) is oscillating, the signal at point (A) of the clamp circuit (2), that is, the input signal to the clamp circuit (2) becomes the signal shown in FIG. 2 (A). A case will be explained below.

The time constant when discharging the capacitor (22) of the first circuit (20) in the clamp circuit (2) (mainly determined by the leakage between the base and emitter of the diode (25) and the transistor (25)), and the second circuit The time constant when discharging the capacitor (26) in (21) (mainly the diode (2
8) and the leakage between the collector and base of the transistor (23)) is larger than the oscillation frequency of the AND operation oscillator (1), the signal at point (b) ) is positively clamped by the second circuit (21), each time the input signal to the clamp circuit (2) reaches a predetermined level (e), the power supply voltage (E
), the signal changes by the level (e) of the input signal as shown in Figure 2 (b), and the signal at point (c) changes to the same level while being clamped to the ground potential (0). The second one that changes negatively every time it changes by (e)
The signal will be as shown in Figure (C). Since this negative signal is input between the base and emitter of the transistor (23), the transistor (23) is switched by the negative signal. Here, the transistor (23) is the first
It operates as a switch circuit that is switched by the input signal of the circuit (20), that is, the negative clamp signal. The signals in FIG. 2 (b) and (c) have mutually inverted phases, so 1, the first circuit (20) and the second circuit (21)
Since the output of the second circuit (21) is attenuated by the resistor (27), the signal at the connection point (d) of the second circuit (21) is attenuated by the resistor (27).
If the clamp output in 1) is △e, then the ground is E+e.
+80) However, Fig. 2 (
The signal shown in (d) will be obtained. This signal is clamped to the level (E) as a signal at the output side point (E) of the capacitor (30) of the rectifier circuit (3) and changes by (E+e) to the signal shown in FIG. 2 (E). terminal (T5
．． An output obtained by rectifying the oscillation output of the AND operation oscillator (1) is generated at T6).

Next, in this AND circuit, the terminal (T1) or
2) Due to changes in the input signal to the AND operation oscillator (
1) When the DC output level changes from the earth level (0) to a predetermined level (e) as shown in Figure 3 (a), and then from the power supply potential (E) to the earth level (0) I will explain about it.

The repetition of the change in the DC output level causes the clamp circuit (
2) in the first and second circuits (22, 2)
If the discharge time constant is longer than the discharge time constant of 6), the signal of turn-on, C) becomes the signal shown in FIG. 3 (C, C). For this reason, the point (
The signal in (d) becomes the signal shown in Figure 3 (d) in which the noise on the positive side is significantly attenuated by the resistor (27), and the rectification time constant of the rectifier circuit (3) (rectifier load and capacitor (30)
) is sufficiently smaller than the rising time constant in Figure 3 (d) (the frequency of the AND operation oscillator is sufficiently high), the signal at point (E) becomes the signal shown in Figure 3 (E). As a result, it is rarely expressed. In other words, the signal at point (E) is generated by clamping the output signal of the logic operation oscillator (1) to the potential (negative) of the terminal (T4) by the first circuit (20), and making the rectifier circuit (3) positive. Since the signal is clamped, the signal shown in FIG. 3 (e) is obtained from which noise on the positive side has been removed. This is a rectifier circuit (3) that converts the output of the AND operation oscillator (1).
Since the input signal (DC signal) that changes positively becomes noise, the AND operation oscillator (
This means that a negative clamp circuit, ie, the first circuit (20), which clamps a signal that changes positively, is inserted between the circuit 1) and the rectifier circuit (3).

The second circuit (21) of the clamp circuit (2) is a rectifier circuit (
3) has the function of increasing the input signal by E. If the first circuit (21) were not present, the input signal to the rectifier circuit (3) would be only the output (e) of the first circuit (20), without the signals in Figures 2 and 3. Time level (E
> becomes zero, and △e does not occur. Therefore, the second circuit (
21) may be omitted, and if the second circuit (21) is omitted, the first circuit (21) may be omitted, as shown by the dotted line in FIG.
If we also omit the resistor (23) and transistor <24) in 20) and directly connect the connection point of the capacitor (22) and diode (25) to the input terminal of the capacitor (30) of the rectifier circuit (3), good.

Next, another embodiment shown in FIG. 4 will be described.

In the AND circuit shown in FIG. 4, the rectifier circuit (3) is connected to the ground terminal (T4) of the power supply to perform negative rectification. This AND circuit connects the first circuit (20) to the positive terminal (T3) of the power supply (E) and the second circuit (21) to the ground terminal (T4).
The configuration is the same as that of the AND circuit shown in FIG. 1, except that it is connected to the AND circuit of FIG.

Therefore, in this AND circuit, when the DC output level of the AND operation oscillator (1) changes, the signal changes from the power supply (
E) and at the same time the noise on the negative side increases by the resistance (27)
The output signal of the AND operation oscillator (1) is significantly attenuated by the first circuit (20), and the negative noise is
Since it is clamped to the potential of T3), it is removed, and the output of the rectifier circuit (3) is not affected by noise.

In the above embodiment, the input signal to the terminal (TI, T2) is positive, but the present invention can also be applied to a case where the input signal to the terminal (TI, T2) is negative. In this case, for example, a negative power source is used as the power source (E),
The terminal (T3) is set to the negative side, and the PNP type transistor is connected to the N
Insert an NPN type transistor into a PN type transistor.
The clamp circuit (2) and rectifier circuit (3) shown in FIG. 1 or 4 may be connected to each of the NP-type transistors.

Effects of the Invention As described above, the present invention provides a clamp circuit on the signal input side of the rectifier circuit that clamps the input signal to the rectifier circuit to the potential of the terminal that is not connected to the rectifier circuit among the power supply terminals. The output of the rectifier circuit is not affected by spike N noise caused by changes in the output level of the AND operation oscillator.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the first embodiment of the AND circuit according to the present invention, Fig. 2 is an explanatory diagram of electrical signals at each point when the AND operation oscillator is oscillating, and Fig. 3 is a diagram showing the logic FIG. 4 is an explanatory diagram of electrical signals at various points when the DC output level of the product operation oscillator changes, and is a diagram showing another embodiment of the AND circuit according to the present invention. (1): AND operation oscillator, (2): Clamp circuit, (3): Rectifier circuit. Patent applicant Nippon Signal Co., Ltd.

Claims (1)

[Scope of Claims] (1) Comprising an AND operation oscillator and a rectifier circuit connected to one terminal for a power supply and rectifying the output signal of the AND operation oscillator, which is turned on and off by the output signal. An AND circuit characterized in that a clamp circuit that is turned off and clamps the output signal to the potential of the other terminal for the power supply is provided on the signal input side of the rectifier circuit. It is characterized by a first circuit that is turned on and off by the output signal of the AND operation oscillator and clamps the output signal to the potential of the other terminal for power supply, and a second circuit that clamps the output signal to the potential of one terminal for power supply. The AND circuit according to Claim 1. [3] The AND circuit according to Claim 2, wherein the second circuit is a circuit having a resistor on the signal output side.