JPS60226128A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance uniformity of etching rate and prevent generation of groove in the flattened etching by adding the process for annealing silicon nitride film deposited on the lower layer Al wiring. CONSTITUTION:After forming a predetermined Locos oxide film, a gate oxide film, polysilicon gate, source drain diffusion layer on a silicon substrate 1, a PSG film 2 of inter-layer insulation film is formed, a contact window is opened and then a lower Al wiring 3 is formed. Next, after depositing a silicon nitride film 4 by plasma vacuum deposition method, the annealing process is carried out within the mixed gas of N2, H2. After, the surface is coated with the photo resist 5 by the rotary coating method, solvent within the photo resist 5 is removed by heat processing. The photo resist 4 is perfectly removed by the etching under the etching condition that the etcthing rate of photo resist 5 and silicon nitride film 4 becomes equal and uneven surface generated by the lower Al wiring is flattened. In this case, the silicon nitride 4 is also partly etched. As the etching gas, CF4/O2 mixed gas is used.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for flattening the surface of a coating in the same device.

Conventional structure and its problems Conventionally, as an example of flattening technology, there is a reflow technique that flattens the surface by heating and melting a phosphosilicate glass (hereinafter referred to as PSG) film, but the heating temperature is high. for,
In this processing step, the impurities in the source/drain diffusion layer are redistributed and the depth of the diffusion layer becomes deeper, so that the short channel effect becomes a problem in VLSI devices where the channel length of the device is 2 μm or less. In addition, with regard to multilayer wiring technology required for higher integration and higher speed semiconductor devices,
When / is used, high temperature is required to flatten the surface of the PSG forming the interlayer insulating film between the upper layer and the lower layer A4 wiring, and the flow technique cannot be applied. There are various techniques for flattening devices at relatively low temperatures, an example of which is shown in Figure 1a.
This will be explained using the process flow chart of d.

In addition, Figure 1 shows the step in which planarization is most required in the M4 multilayer wiring technology, that is, the planarization of the insulating film (interlayer insulating film) covering the lower layer A/wiring required when forming the upper layer A71 wiring. For the sake of simplicity,
A cross section of the transistor region is intentionally not shown.

As shown in the figure, first, circuit elements (
After providing an interlayer insulating film 2 made of PSG (not shown) and PSG, a lower layer A7 with a film thickness of 0.8 μm, for example! Wiring 3 is formed (FIG. 1a).

Thereafter, a silicon nitride film 4 with a thickness of 1.0 μm, for example, is deposited by plasma deposition (FIG. 1b).

Furthermore, a photoresist 5 is spin-coated on this silicon nitride film 4 (FIG. 1C).

Next, heat treatment is performed at about 200"C to remove the solvent in the photoresist 5, and then CF410 is used as an etching gas.
2, the photoresist 6 is completely etched away under conditions such that the etching rates of the silicon nitride film 4 and the photoresist 6 are approximately the same. At this time, there are 7 in the lower layer.
! A portion of the silicon nitride film 4 deposited on the wiring 3 is also etched at the same time, and the etching is completed when a small amount of the silicon nitride film remains on the lower layer Aβ wiring 3 (FIG. 1d).

This completes the planarization process, and after that, an interlayer insulating film between the lower layer Al wiring and the upper layer E wiring, through holes, and upper layer A/wiring are formed to complete the A/2 layer wiring structure. , in this case, the photoresist 6 and the silicon nitride film 4
In the process of simultaneously etching the lower layer interconnect 3
The silicon nitride film 4 is rapidly etched along the sidewalls of the wafer, resulting in grooves 6 as shown in FIG. 1d. If such a groove is formed, it is a problem that the upper layer wiring is likely to be disconnected when the upper layer wiring is formed later. The reason for the formation of these grooves is that when a silicon nitride film is deposited by plasma evaporation, the stress in the silicon nitride film increases at the corner between the lower layer Al wiring and the silicon substrate surface, and during etching,
This is because this part is rapidly etched.

Note that the depth of the generated groove is determined by the etching pressure of 500 m.
When the torr is Q, 5 μm, when the r-7 ting pressure is 100 mtorrO, it is 0.2 μm. Note that the former is isotropic etching, and the latter is anisotropic etching. Thus, the groove depth becomes particularly large during isotropic etching.

OBJECTS OF THE INVENTION The present invention solves these problems and provides a method for manufacturing a semiconductor device in which no grooves are formed along the lower layer A4 wiring, that is, smooth planarization is possible.

Structure of the Invention The present invention adds a step of annealing the silicon nitride film deposited on the lower layer interconnect, thereby reducing the stress on the silicon nitride film and improving the uniformity of the etching rate during planarization etching. This prevents the occurrence of high grooves.

DESCRIPTION OF EMBODIMENTS As an example, in the mu 12 layer wiring technology, the present invention
A, - M using the flattening method of All Z'l
An example of a method for manufacturing an O8 type semiconductor device is shown in FIGS. 2a to 2d.
This will be explained using the process flowchart. For the sake of simplicity, only the A12 layer wiring portion is shown in the figure, and a cross section of the transistor region is intentionally not shown.

As shown in the figure, first, a predetermined Lo
After forming a cos oxide film, a gate oxide film, a polysilicon gate, and a source/drain diffusion layer, a PSG film 2, which is an interlayer insulating film, is formed to cover these films, and a contact window is opened. A lower layer β wiring 3 having a thickness of 8 μm is formed (FIG. 2a).

Next, a silicon nitride film 4 with a thickness of 1.0 μm was deposited by plasma deposition at a processing temperature of 330'C, and then N2.
Anneal at 450″C in H2 mixed gas [
Figure 2b]. Subsequently, a photoresist 5 is spin-coated thereon, and then a heat treatment is performed at, for example, 200° C. to almost completely remove the solvent in the photoresist 6 (FIG. 2C).

Next, the photoresist 4 is etched under etching conditions such that the etching rate of the photoresist 5 and the silicon nitride film 4 are the same.
Completely remove the surface by etching and flatten the unevenness caused by the underlying uneven wiring. Incidentally, at this time, a part of the silicon nitride film 4 is also etched at the same time.

A C1F410□ mixed gas is used as the etching gas, and the 02 concentration is determined so that the etching rate ratio of the photoresist 5 and the silicon nitride film 4 is 1 [Figure 2 d]
. This completes the planarization process, and later, an interlayer insulating film between the lower layer A71 wiring and the upper layer I wiring, through holes, and upper layer A7 wiring are formed to complete the A71!27 wiring structure.

Effects of the Invention According to the present invention, since the annealing treatment is performed after the silicon nitride film is deposited, stress on the silicon nitride film at the corners of the lower layer A4 wiring and the substrate surface is reduced, so that less stress is applied during etching for planarization. The silicon nitride film is etched uniformly, and the occurrence of grooves can be considerably suppressed. In the case of this example, in the case of isotropic etching conditions with an etching pressure of 500 mtorr, the depth of the groove is α1 μm, and the etching pressure is 100 mtorr.
In the case of mtorr anisotropic etching conditions, no groove generation occurred.

In this experiment, a silicon nitride film was deposited on the lower i-wire, but it is clear that similar effects can be expected when a silicon oxide film or a pse film is used.

In addition to heat treatment, annealing by irradiation with a charged beam of ions, electrons, etc. is also effective as a means of annealing the insulating film deposited on the lower Al wiring.

[Brief explanation of the drawing]

1A-6 are flowcharts showing the manufacturing process for explaining the prior art, and FIGS. 2A-2D are flowcharts showing the manufacturing process for explaining one embodiment of the present invention. 1... Silicon substrate, 2. River... PSG, 3.
...Lower layer A4 wiring, 4... (plasma)
Silicon nitride film, 6... Photoresist, 6...
···groove. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

[Claims] (1) A step of depositing an insulating film on a semiconductor substrate provided with circuit elements or electrodes and a wiring film, a step of annealing the insulating film, and a step of applying an organic resin on the insulating film. and a step of etching a portion of the organic resin and the insulating film under etching conditions such that the etching rate of the applied organic resin and the insulating film are approximately the same. Method of manufacturing the device. ? 2. The method of manufacturing a semiconductor device according to claim 1, wherein the annealing treatment of the insulating film is a heat treatment at a temperature above the insulating film deposition temperature and below the deterioration temperature of the semiconductor element. (3) It is specified that the annealing treatment of the insulating film is annealing by irradiation with a charged beam of ions, electrons, etc.
J-2, method of manufacturing the ``Kyoutsudo Fushimito''.